JPH02198375A - Testing apparatus of ic - Google Patents

Abstract

PURPOSE:To adjust the delay time with high accuracy by providing a variable delay circuit in each distributer of a reference signal distributer, a switch for taking out a reference signal from an input side of each pin electronics card and a feed-back circuit. CONSTITUTION:Variable delay circuits 42A-42I are respectively provided in distributers of a reference signal distributer 40. At the same time, a switch 50 for selectively taking out a reference signal input to each logic comparator 22 of pin electronics cards 20A-20I and a feed-back circuit 51 for feeding the taken-out reference signal back to an input side of the distributer 40 are provided, thereby constituting a closed-loop oscillating circuit. The switch 50 is switched and the delay amount of the circuits 42A-42I is adjusted to make constant the oscillating frequency of the closed loop for each card 20A-20I. Accordingly, the delay time of all the logic comparators 22 of the cards 20A-20I can be correctly adjusted, so that the IC can be tested with high reliability.

Description

DETAILED DESCRIPTION OF THE INVENTION "Field of Industrial Application" The present invention relates to an IC testing device for testing an IC such as a memory.

"Prior Art" FIG. 3 shows a conventional IC testing apparatus, and numeral 10 in FIG. 3 indicates an IC to be tested. One pin electronics card 2OA, 20B, 20C, . . . is connected to each terminal of the ICl0 under test. Therefore, at least as many pin electronics cards 20A, 20B, 20C, . . . as there are terminals of the IC under test are prepared.

Each pin electronics card 20A, 20B, 2
0C... is a drive circuit 21 that provides a drive signal to each terminal of the ICl0 under test, and a response output signal outputted to each terminal of the ICl0 under test that checks whether or not it has a normal logic level. A comparator 22 that makes a determination and captures the information is implemented. Note that 23 is a resistor that serves as a pseudo load and a terminating resistor for the ICl0 under test, and 24 is a mode changeover switch that switches between the calibration mode and the test mode.

In the test mode, the mode changeover switch 24 is controlled to be off, and in this state, a drive signal is input from the test device 15 to the drive circuit 21 through the variable delay circuit 31, and
The response output signal of the ICl0 under test outputted from the comparator 22 is taken out through the variable delay circuit 32 and sent to the test device 1.
15, and the quality of the ICl0 to be tested is determined.

In the mode under test, the phases of the drive signals applied to each terminal of the ICl0 under test must match, and the IC under test
The fact that the response output signal output from l0 is not given a different amount of delay for each pin electronics card
This type of IC test equipment is required.

For this, each pin electronics card 20A
20B, 20C... variable delay circuit 31.3
2 is provided, and the delay amount of these variable delay circuits 31 and 32 is adjusted to match the phase of the drive signal and the phase of the response output signal for each pin electronics card.
adjustments will be made.

This adjustment to match the phases is called timing calibration or skew adjustment and is performed periodically between tests.

Conventional timing calibration is performed as follows. Each pin electronics card 2OA, 20B.

Mode changeover switch 24 mounted on 20C...
is turned on, and in this state, each pin electronics card 2OA is connected from the test device 15 through the distributor 40.
, 20B, 20C, . . . are provided with a timing calibration reference signal R3.

The timing calibration reference signal R3 is taken out to the test device 15 through the logic comparator 22 and the variable delay circuit 32, and is sent to each pin electronics card 20A, 20B, 20C.
For each pin electronics card 20A, 20B, 20, the phase of the extracted calibration signal is
The variable delay circuit 32 is adjusted so that they all have the same phase every time C. With this adjustment, each pin electronics card 20A, 20B, 20C...
The timing of the system of each logical comparator 22 is calibrated.

Incidentally, the adjustment of the variable delay circuits 31 and 32 is performed by outputting the phase measurement result outputted from the test device 15 as a digital signal, and setting the digital signal in the variable delay circuits 31 and 32 to automatically adjust it.

Next, a drive signal is given to the drive circuit 21, and this drive signal is taken out through the logic comparator 22 and the variable delay circuit 32,
The variable delay circuit 31 is adjusted so that all the phases match, and the timing of the drive circuit system is calibrated.

"Problem to be Solved by the Invention" The reference signal distributor 40 includes a buffer 41A in each distribution path for distributing the calibration reference signal R3 to each pin electronics card 20A, 20B, 20C, . . . .

41B, 41C... are arranged.

Buffers 41A, 41B, 41C... and reference signal distributor 40 and pin electronics card 20A
.

If there is a difference in delay time between the wiring portions 20B, 20C, .

In other words, even if there is a phase difference between the reference signals supplied to the logic comparator 22 using the conventional calibration method, the phase difference is corrected by the variable delay circuit 32 and eventually the input of the reference signal distributor 40 and the variable delay circuit 32 It is calibrated so that the sum of the delay between the output of

The delay amount of the variable delay circuit 32 calibrated in this way includes the delay error of each distribution path of the reference signal distributor 40.

A first object of the present invention is to provide an IC testing device that can calibrate delay errors in a reference signal supply path, that is, each distribution path of the reference signal distributor 40, and can perform correct timing calibration.

A second object of the present invention is to provide an IC testing device that can accurately calibrate the timing of a drive circuit system.

A third object of the present invention is to provide an IC testing device that can easily calibrate the timing of a reference signal supply path or drive circuit system.

"Means for Solving the Problems" In the first invention of this application, a variable delay circuit is provided in each distribution path of a reference signal distributor, and a changeover switch is provided to take out a reference signal for calibration from the input side of each pin electronics card. The reference signal taken out by this changeover switch is fed back to the input side of the reference signal distributor, and this feedback forms a closed loop oscillation circuit, so that the oscillation frequency of the closed loop oscillation circuit is constant for each pin electronics card. The configuration is such that the delay amount of the variable delay circuit provided in each distribution path is adjusted.

According to the configuration of the first invention, since the delay amount of the reference signal supply path is calibrated to be a constant value, it is possible to provide each pin electronics card with a reference signal without phase difference.

As a result, after calibrating the delay amount of the reference signal supply path,
By adjusting the amount of delay in the path of the logical comparator, the amount of delay in the path of the logical comparator can be calibrated correctly.

Furthermore, since the delay amount of the logic comparator can be calibrated correctly, the drive circuit that is calibrated using this can also be calibrated correctly.

Therefore, according to the first aspect of the invention, there is provided an IC testing apparatus that has a small phase error in the drive signal applied to the IC under test, and can also input the response output signal output from the IC under test into the test apparatus without causing a timing error. can be provided.

In addition, according to the I(j&experiment) device of the present invention, a feedback oscillation circuit is configured for each distribution path, and the delay amount of a variable delay circuit provided in each distribution path is adjusted so that the oscillation frequency of this feedback oscillation circuit is constant. Since the structure is such that the delay amount of each distribution path is adjusted to a constant value, calibration can be performed in a short time and with high accuracy.

In the second invention of this application, a changeover switch is provided on the output side of the drive circuit, and the changeover switch selectively takes out the drive signal output from the drive circuit of each pin electronics card, and the selected and taken out drive signal The signal is fed back to the reference signal generator, and a closed loop oscillation circuit is constructed by the drive circuit system.

By measuring the oscillation period of the closed loop oscillation circuit configured by this drive circuit system, it is possible to measure the delay time of the drive circuit system of each pin electronics card.
It can be adjusted to a specified delay time.

Therefore, according to the second invention, the delay amount of the drive circuit of each pin electronics card can be corrected to a specified value, and highly accurate timing calibration can be performed.

As described above, according to the first and second inventions of this application, since the delay time of the circuit is measured based on the closed loop oscillation period, it is possible to measure the delay time with high accuracy.As a result, the drive signal applied to the IC under test phase and IC under test
It is possible to match the phases of the response signals with high precision, thereby providing an IC test device with high reliability.

"Example" FIG. 1 shows an embodiment of the first invention of this application.

In the figure, 10 is the test object 1c, 15 is the test device 20A.

20B 20C... are pin electronics cards, 31.32 are variable delay circuits, and 40 are timing calibration reference signals R3 for each pin electronics card 2.
The reference signal distributor that distributes to 0A, 2()B, 20C, . . . is shown as in the conventional example.

The first invention of this application is characterized in that a variable delay circuit 42A is provided in each distribution path of the reference signal distributor 40.

42B 42C...421 is provided, and
Each pin electronics card 20A, 20B, 20C
. . . A changeover switch 50 for selectively taking out the reference signal input to the switch 201 and a feedback path 51 for returning the reference signal taken out by the changeover switch 50 to the input end of the distributor 40 are provided. be.

The feedback FIR 51 is connected to one input terminal of, for example, an OR circuit 15A provided inside the test device 15.

The other input terminal of the OR circuit 15A is connected to the reference signal generator 1.
A reference signal R3 is given from 5B. The output of the OR circuit 15A is given to the distributor 40.

In the calibration mode for calibrating the reference signal supply path, the mode selector switch 24 is set to OFF, and the selector switch 50 switches the pin electronics cards 20A, 20B, 20C.
... any one input terminal A, B, C of 201
...Select bow 0 Selected pin electronics card 20A, 20B, 20C...201
The input terminals A, B, C, . . . are connected to one input terminal of the OR circuit 15A through the feedback circuit 51, forming a closed loop.

By applying one pulse with a pulse width shorter than the delay time in the loop from the reference signal generator 15B to this closed loop, this pulse is fed back to the OR circuit 15A after the delay time in the loop has elapsed, and is sent back to the distributor. given to 40. Therefore, the pulse circulates at a period of delay time T8 within the loop, and a closed loop oscillation circuit is constructed.

The delay time of this closed loop can be measured by measuring the period TI of the pulses oscillated by this closed loop oscillation circuit. Reference numeral 15c indicates a period (or frequency) measuring device, and the period TK of the pulse is measured by this period measuring device 15C. This pulse period measuring device 15
C does not necessarily need to be built into the test device 15, and may be connected to the outside as necessary.

When a closed loop is configured in this way and one pulse is input to this closed loop, this pulse circulates within the closed loop, and the delay time within the closed loop is measured by measuring the period T of the circulating pulse. be able to.

Therefore, by sequentially switching the switching switch 50 to configure a closed loop for each pin electronics card 20A to 201, and measuring the oscillation period of each closed loop, the delay amount of the reference signal distribution path included in each closed loop can be measured. Can be done. Therefore, the oscillation frequency y4T of each closed loop
Variable delay circuits 42A and 42B are provided in each reference signal distribution path so that I is constant.

By manually or automatically adjusting the delay amount of 42C...421, the delay time of each reference signal distribution path can be made uniform to a constant value.

After aligning the delay times of each reference signal distribution path to zero, turn on the mode selector switch 24, calibrate the timing of the logic comparator 22 path, and you are ready for logic comparison! The path 322 can make the delay times of the logic comparators 22 of all the pin electronics cards 20A to 201 uniform to a constant value without being affected by variations in the delay times of the reference signal distributor 40.

FIG. 2 shows an embodiment of the second invention of this application.

In this example, a case is shown in which timing is calibrated for the drive circuit 21 that provides a drive signal to the ICl0 under test. Therefore, a closed loop is constructed using the signal path of the drive circuit 21, and the loop oscillation period of this closed loop is measured to measure the delay time of the drive circuit.The variable delay circuit 3
1 is configured to adjust.

To express the system of the drive circuit 21 in detail, as shown in FIG. 2, a flip-flop 25 is provided on the input side of the drive circuit 21, and set and reset signals are applied to the set terminal S and reset terminal R of the flip-flop 25. is given, is converted into a real waveform by the flip-flop 25, and this real waveform signal is given to the drive circuit 21.

The reference signal generator 15B outputs a clock A and a clock B, and the clock A and the clock B are sent to the variable delay circuits 31A and 31 through a format control circuit 60.
Give to B. Variable delay circuits 31A and 31B provide clock A and clock B to flip-flop 25 as set signals and reset signals.

Here, in this second invention, each pin electronics card 20A is controlled by the changeover switch 50.

The drive output signals of the drive circuits 21 of 20B, 20C, .

When the reference signal generator 15B receives the drive output signal,
Clock A and clock B are output in synchronization with the leading and trailing edges. In this way, the drive system is operated as a closed loop oscillation circuit.

The period measurement circuit 15C measures the loop oscillation period Tw and sends the measurement result to the test processor 61. The test processor 61 uses the period measurement value to determine the variable delay circuit 31A,
The amount of deviation of the delay time of 31B from the reference value is calculated, and correction data corresponding to the amount of deviation is output. This correction data is given to the variable delay circuits 31A and 31B, and the delay time is controlled to be a prescribed reference value.

Therefore, with this configuration, the delay time of the drive signal path can be corrected accurately (and automatically corrected).

Effects of the Invention As described above, according to the present invention, the delay time of the circuit can be measured by connecting the circuit whose delay time is to be measured in a closed loop and causing loop oscillation within the closed loop. This measurement provides highly accurate measurement results.

In particular, according to the first invention, since the highly accurate measuring method is used to correct the variation in the delay time of the reference signal distribution path, each pin electronics card 20A~
All the reference signals input to 201 can be made to have the same phase. Therefore, by adjusting the delay time of the logic comparator 22 using this reference signal, the path of the logic comparator 22 can be correctly adjusted for each pin electronics card. As a result, the test of ICl0 to be tested can be conducted with high reliability.

Further, according to the second invention of this application, since the delay time of the drive circuit 21 is measured using closed loop oscillation, the accuracy of the measurement is high.Therefore, according to the second invention, the delay time of the drive circuit system is high. It is possible to adjust the variation in accuracy with high precision, and as a result, the reliability of the test of the IC under test can be improved.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing an embodiment of the first invention of this application, Fig. 2 is a block diagram showing an embodiment of the second invention of this application, and Fig. 3 is a block diagram for explaining the conventional technology. It is. lO: IC under test 115: Test equipment, 20A, 20B
...20I: Pin electronics card, 2
1: Drive circuit, 22: Logic comparator, 24: Mode changeover switch, 31, 32, 42A, 42B. ...42I: Variable delay circuit, 40: Reference signal distributor, 50: Changeover switch, 51: Feedback path.

Claims (2)

[Claims] (1) A drive circuit that provides a drive signal to the IC under test, and a logic comparator that determines whether the response output signal of the IC under test has a normal logic level and takes in the response signal that has the normal judgment level. , a pin electronics card mounted with a variable delay circuit provided on the output side of the logic comparator and adjusting the delay amount error of each logic comparator is the pin electronics card under test.
In the calibration mode, the logic comparator of each pin electronics card is provided with a reference signal from the reference signal generator through the distributor, and the output signal of the logic comparator is taken out through the variable delay circuit. In an IC test equipment configured to adjust the delay amount of the variable delay circuit of each pin electronics card so that the phase of the output signal of the circuit matches each pin electronics, a variable delay circuit is installed in each distribution path of the distributor. In addition to providing
A changeover switch is provided to selectively branch and take out the reference signal input to the logic comparator of each pin electronics card, and the reference signal taken out by this changeover switch is fed back to the input side of the distributor, and this feedback causes oscillation. Configure a loop and change the changeover switch to adjust the delay amount of the variable delay circuit described above so that the oscillation frequency in the state including each pin electronics card is a constant value, and by adjusting the delay amount, the An IC test device configured to remove delay errors in a reference signal transmission path. (2) A drive circuit that provides a drive signal to the IC under test, and a logic comparator that determines whether the response output signal of the IC under test has a normal logic level and takes in the response signal that has the normal judgment level. , in an IC test equipment in which pin electronics cards mounted with variable delay circuits connected to the path of the above-mentioned drive circuit are installed in a number equal to or greater than the number of terminals of the IC under test, on the output side of each drive circuit of the above-mentioned pin electronics card. A changeover switch is connected, and the changeover switch is configured to selectively take out the output of the drive circuit of each pin electronics card, and the drive signal taken out by the changeover switch is fed back to the reference signal generator. A feedback oscillation circuit is configured, the oscillation period of this feedback oscillation circuit is measured, the delay time of the drive signal path is measured, and this period measurement result is used to calculate the delay of the variable delay circuit provided in the path of the drive circuit. An IC testing device that controls time and eliminates delay time errors in the drive circuit system of each pin electronics card.