JPH0519027A - Semiconductor logic integrated circuit - Google Patents

Abstract

PURPOSE:To enable a delay to be judged in a short time by a single test pattern and a program when performing test with an external tester. CONSTITUTION:An IC chip 20 is provided with an internal logic circuit 19 and a test circuit portion 18 independently. The test circuit portion 18 has a delay-time measurement circuit 10 which outputs a counter output S9 having a counter 2 for inputting an oscillation output signal S8 of a conventional ring oscillator 1 for monitoring to an input clock terminal C and a counter instruction signal S5 to a terminal L and a comparator 11 which compares the counter output signal S9 with a reference value S6 which is input from an outside and then outputs a delay over signal S11 to the outside.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor logic integrated circuit, and more particularly to a semiconductor logic integrated circuit incorporating a monitor delay circuit for determining variations in delay time caused by manufacturing variations.

[0002]

2. Description of the Related Art As shown in FIG. 4, the delay time of a conventional monitor delay circuit of a semiconductor logic integrated circuit of this type is measured as follows.
The oscillation output signal S8 of the ring oscillator 1 for monitoring built in the IC chip 20b is output from the output terminal T8, and the oscillation output signal S8 is sampled using an external tester to determine the oscillation frequency of the ring oscillator 1. The delay characteristic of the internal logic circuit 19 is determined by monitor measurement.

That is, when the IC chip 20b causes a product difference in the delay characteristics of the internal logic circuit 19 due to the variation in the conditions in the manufacturing process, the delay characteristics of the monitor ring oscillator 1 in the same IC chip 20a are tested. This means that the internal logic circuit has been fully monitored.

[0004]

In this conventional semiconductor logic integrated circuit, in order to test the delay time of the ring oscillator for monitoring, the output signal is asynchronously sampled by an external tester so that the tester is controlled. Not only is the program complicated, but the test time is long.

[0005]

A semiconductor logic integrated circuit of the present invention provides a ring oscillator for outputting an oscillation output signal having an oscillation frequency corresponding to a delay time characteristic of an internal logic circuit on the same chip, and the oscillation output signal. A delay time measuring circuit having a counter for inputting a counting instruction signal as a clock signal and counting within a predetermined time and outputting a counter output signal, a value of the counter output signal and a predetermined delay time reference value And a delay time determination circuit that outputs a delay over signal by comparing

[0006]

The present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of a first embodiment of the present invention, and FIG. 2 is a timing chart of each signal for explaining the operation of the block of FIG. As shown in FIG. 1, the IC chip 20 has a test circuit section 18 independent of the internal logic circuit 19.
The test circuit section 18 has a counter 2 for inputting the oscillation output signal S8 of the conventional monitor ring oscillator 1 of FIG. 4 to the input clock terminal C and a counting instruction signal S5 to the terminal L, and outputs a counter output S9. Delay time measuring circuit 10
And the counter output signal S9 and the reference value S input from the outside.
6 and the comparator 11 which outputs the delay over signal S11 to the outside.

As shown in FIG. 2, when the oscillation control signal S4 is at "H" level, the oscillation output signal S8 oscillates. The counter 2 performs a count-up operation using the oscillation output signal S8 as an input clock, but performs a count-up operation only while the count instruction signal S5 input to the count instruction terminal T5 is at "H" level, and the count instruction signal S5 is " The counter output signal is "0" during the L "level.

The counter output signal S9 is input to the comparator 3 and compared with the reference value S6 input to the reference value input terminal T6. At this time, the counter output signal S is more than the reference value S6.
At the time t1 when the value of 9 becomes large, the comparator 3 changes the delay time over signal S11 from the "L" level to the "H" level and outputs it to the delay time over signal output terminal T7.

The external circuit connected to the output terminal T7 recognizes the delay time over signal S11 at the timing of the rising time t2 of the counting instruction signal S5, and thereby the IC chip 2
The delay characteristic of the internal logic circuit 19 of 0 can be determined.

FIG. 3 is a block diagram of a second embodiment of the present invention. When the semiconductor logic circuit is an IC chip 20a used in a microprocessor system or the like, the test circuit unit 18a has an instruction decoder 12 connected to a processor bus 16 for an oscillation control signal S4 and a counting instruction to a register 13 and a register 14, respectively. The signal S5 is instructed to be turned on or off. Then, the register 15 is instructed to write the reference value via the processor bus 16.

The operations of the monitor ring oscillator 1, the counter 2 and the comparator 3 are the same as those in the first embodiment. Then, the delay time over signal 11 is output to the processor bus 16. As a result, it is possible to monitor and determine the delay time of the internal logic circuit from outside the IC chip 20a via the processor bus 16.

In this case, it is economical because the test external input terminals T5 and T6 can be formed without the addition as in the first embodiment.

[0013]

As described above, according to the present invention, a monitor ring oscillator that oscillates at a frequency corresponding to the delay time of the elements of the IC chip, and its oscillation output signal are input as a clock signal, and within a predetermined time. The delay time measuring circuit having a counter that counts at, and the test circuit section of the delay time determining circuit that compares a designated value with a counter output value in the delay time measuring circuit and outputs a comparison result.

Therefore, according to the present invention, the delay can be determined in a short time by a simple test pattern and program when testing with an external tester.

[Brief description of drawings]

FIG. 1 is a block diagram of a first embodiment of the present invention.

FIG. 2 is a timing chart of each signal for explaining the operation of the block of FIG.

FIG. 3 is a block diagram of a second embodiment of the present invention.

FIG. 4 is a block diagram of an example of a conventional semiconductor logic integrated circuit.

[Explanation of symbols] 1 Monitor ring oscillator 2 counter 3 comparator 10 Delay time measurement circuit 11 Delay time judgment circuit 12 Instruction decoder 13, 14, 15 registers 16 processor bus 18 Test circuit section 19 Internal logic circuit 20,20a IC chip T4 oscillation control terminal T5 counting instruction terminal T6 reference value input terminal T7 delay time over signal output terminal S8 oscillation output signal S9 counter output signal S11 Delay time over signal

Claims (2)

[Claims] 1. A ring oscillator which inputs an oscillation control signal and outputs an oscillation output signal having an oscillation frequency corresponding to a delay time characteristic of an internal logic circuit on the same chip and a counting instruction using the oscillation output signal as a clock signal. A delay time measuring circuit having a counter for respectively inputting signals and counting within a predetermined time and outputting a counter output signal, and comparing the value of the counter output signal with a predetermined delay time reference value for delay over A semiconductor logic integrated circuit, comprising: a delay time determination circuit that outputs a signal. 2. A semiconductor logic integrated circuit according to claim 1, further comprising an instruction decoder connected to the processor bus, and a register for outputting the oscillation output signal and the counting instruction signal under the control of the instruction decoder.