JP2008172328A - Voltage comparison circuit, and power supply control circuit employing it - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a voltage comparison circuit which can compare a plurality of voltages with a plurality of reference voltages. <P>SOLUTION: The voltage comparison circuit 100 compares a plurality of input voltages Vin1-Vinn with threshold voltages Vth1-Vthn set respectively and judges the relation of magnitude. A plurality of pairs of voltage division resistor RP1-RPn divide the plurality of input voltages Vin1-Vinn at voltage division ratios r1-rn set respectively to produce a plurality of division voltages Vd1-Vdn. A reference voltage source 10 generates an adjustable reference voltage Vref. A plurality of comparators CMP1-CMPn compare the reference voltage Vref with the plurality of division voltages Vd1-Vdn produced by the plurality of pairs of voltage division resistor RP1-RPn, respectively. A plurality of differential pairs provided, respectively, on the input stage of the plurality of comparators CMP1-CMPn are arranged on a semiconductor substrate contiguously to each other. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a voltage comparison circuit, and more particularly to a voltage comparison circuit that compares a plurality of voltages with a threshold voltage set for each voltage to determine a magnitude relationship.

  In various electronic devices such as mobile phones, PDAs (Personal Digital Assistants), and notebook personal computers in recent years, CPUs (Central Processing Units) that perform digital signal processing, other DSPs (Digital Signal Processors), or liquid crystals Many electronic circuits such as panels and LEDs are mounted. These electronic circuit components operate by receiving power supply from a battery or a power supply circuit that stabilizes the battery voltage.

  Here, a stable operation guarantee voltage is defined for each electronic circuit, and when the supplied voltage is equal to or lower than the stable operation guarantee voltage, the electronic circuit does not operate normally. Therefore, in such an electronic device, it is necessary to monitor a voltage supplied to a plurality of electronic circuits in comparison with a predetermined voltage individually set for each, and to control a startup sequence and the like.

  The present invention has been made in view of such a situation, and an object thereof is to provide a voltage comparison circuit capable of comparing a plurality of voltages with a plurality of reference voltages.

  One embodiment of the present invention relates to a voltage comparison circuit that compares a plurality of input voltages with threshold voltages set for each of them and determines a magnitude relationship. This voltage comparison circuit divides a plurality of input voltages by a voltage dividing ratio set to each of them, a plurality of voltage dividing resistor pairs for generating a plurality of divided voltages, a reference voltage source for generating an adjustable reference voltage, And a plurality of comparators respectively comparing the reference voltage with a plurality of divided voltages generated by the plurality of voltage dividing resistor pairs. The plurality of differential pairs respectively provided in the input stages of the plurality of comparators are arranged adjacent to each other on the semiconductor substrate.

In this aspect, when the reference voltage is Vref and the voltage dividing ratios of the plurality of n voltage dividing resistors are r1 to rn, the threshold voltages Vth1 to Vthn for the plurality of input voltages are Vref / r1 to Vref / rn, respectively. Set to Therefore, if the reference voltage Vref is changed, a plurality of threshold voltages for each of the plurality of input voltages can be adjusted.
Here, in general, when a plurality of comparators are provided, only the transistors constituting the differential pair for each comparator are paired, and the plurality of comparators are configured separately and the offset of each comparator varies. . On the other hand, in the present invention, since the differential pairs of the plurality of comparators are arranged adjacent to each other, the pair of differential pairs can be paired, so that the offsets of the plurality of comparators can be made uniform. In other words, it is only necessary to provide an adjustment function for the reference voltage, and it is not necessary to provide the trimming function for the voltage dividing resistor pair, so that the circuit area can be reduced.

In one aspect, a plurality of current mirror loads provided in the current paths of the respective differential pairs may be arranged adjacent to each other on the semiconductor substrate.
In this case, compared with the case where only the differential pair is adjacent, the offset of the comparator can be made more uniform.

A plurality of differential pairs are arranged adjacent to each other in the first direction of the semiconductor substrate, and a plurality of current mirror loads are arranged adjacent to each other in the first direction of the semiconductor substrate. The i-th (i is a natural number) differential pair and the corresponding i-th current mirror load are arranged adjacent to each other in a second direction perpendicular to the first direction.
In this case, since the elements in the same comparator are arranged in the second direction, wiring becomes easy.

In one embodiment, a plurality of resistance load pairs provided in place of the plurality of current mirror loads may be arranged adjacent to each other on the semiconductor substrate.
In this case, compared with the case where only the differential pair is adjacent, the offset of the comparator can be made more uniform.

A plurality of differential pairs are arranged adjacent to each other in the first direction of the semiconductor substrate, and a plurality of load resistance pairs are arranged adjacent to each other in the first direction of the semiconductor substrate. The i-th (i is a natural number) differential pair and the corresponding i-th load resistance pair may be arranged adjacent to each other in a second direction perpendicular to the first direction.
In this case, since the elements in the same comparator are arranged in the second direction, wiring becomes easy.

In one aspect, a plurality of tail transistors that cause tail currents to flow through the plurality of differential pairs may be arranged adjacent to each other on the semiconductor substrate.
In this case, compared with the case where only the differential pair is adjacent, the offset of the comparator can be made more uniform.

A plurality of differential pairs are arranged adjacent to each other in the first direction of the semiconductor substrate, and a plurality of tail transistors are arranged adjacent to each other in the first direction of the semiconductor substrate. The i-th (i is a natural number) differential pair and the corresponding i-th tail transistor are arranged adjacent to each other in a second direction perpendicular to the first direction.
In this case, since the elements in the same comparator are arranged in the second direction, wiring becomes easy.

In one aspect, each of the plurality of voltage dividing resistor pairs may include first and second resistors configured by connecting unit resistor elements in series. The unit resistance elements may be arranged in a concentrated manner on a predetermined region on the semiconductor substrate, and a plurality of voltage dividing resistor pairs may be paired.
In this case, variations in the voltage division ratio are also suppressed, so that variations in a plurality of threshold voltages can be suppressed.

  In one aspect, the reference voltage source may include a reference voltage circuit that generates a predetermined constant voltage, and a reference voltage dividing resistor pair that divides the constant voltage and generates a reference voltage. At least one of the reference voltage dividing resistor pair may be configured to be trimmed.

  In one embodiment, each of the plurality of voltage dividing resistor pairs may include first and second resistors configured by connecting unit resistor elements in series. The reference voltage source may include a reference voltage circuit that generates a predetermined constant voltage, and a reference voltage dividing resistor pair that divides the constant voltage and generates a reference voltage. The reference voltage dividing resistor pair includes first and second reference resistors configured by connecting unit resistor elements in series, at least one of which is configured to be trimmed, and the unit resistor elements are arranged in a predetermined region on the semiconductor substrate. Alternatively, a plurality of voltage dividing resistor pairs and a reference voltage dividing resistor pair may be paired.

  Another aspect of the present invention is a power management circuit. The power management circuit includes a power supply circuit that generates a plurality of voltages, a voltage comparison circuit that compares a plurality of voltages output from the power supply circuit with a plurality of threshold voltages, and a comparison result of the voltage comparison circuit. And a control unit for controlling the operation of the power supply circuit.

  Note that any combination of the above-described constituent elements and the constituent elements and expressions of the present invention replaced with each other among methods, apparatuses, systems, etc. are also effective as an aspect of the present invention.

  According to the voltage comparison circuit of the present invention, a plurality of threshold voltages can be easily adjusted.

  Hereinafter, a low-voltage malfunction prevention circuit according to an embodiment of the present invention will be described with reference to the drawings. The same or equivalent components, members, and processes shown in the drawings are denoted by the same reference numerals, and repeated descriptions are omitted as appropriate.

  FIG. 1 is a circuit diagram showing a configuration of a voltage comparison circuit 100 according to the embodiment. The voltage comparison circuit 100 compares the input voltages Vin1 to Vinn input to a plurality of n (n is an integer of 2 or more) input terminals P1 to Pn with threshold voltages set to the respective input terminals P1 to Pn. Determine. The comparison results are output as comparison signals S1 to Sn, respectively.

The voltage comparison circuit 100 includes a plurality of voltage dividing resistor pairs RP1 to RPn, a reference voltage source 10, and a plurality of comparators CMP1 to CMPn.
The voltage dividing resistor pairs RP1 to RPn divide the plurality of input voltages Vin1 to Vinn at the voltage dividing ratios r1 to rn set respectively, and generate a plurality of divided voltages Vd1 to Vdn. The voltage dividing resistor pair RPi includes a first resistor Ria and a second resistor Rib connected in series. The voltage dividing ratio ri in the i-th voltage dividing resistor vs. RPi is
ri = Rib / (Ria + Rib)
Given in. The voltage dividing resistor pair RP is adjusted to include a fixed resistor whose resistance value cannot be adjusted.

  The reference voltage source 10 generates an adjustable reference voltage Vref. In order to generate the reference voltage Vref, the reference voltage source 10 may be configured as shown in FIG. The reference voltage source 10 of FIG. 1 includes a reference voltage circuit 12 and a reference voltage dividing resistor pair 14.

  The reference voltage circuit 12 is a band gap regulator, for example, and generates a predetermined constant voltage Vbgr. The reference voltage dividing resistor pair 14 includes a first reference resistor R0a and a second reference resistor R0b, and a voltage dividing ratio r0 is set according to the ratio of the resistance values. The reference voltage dividing resistor pair 14 divides the constant voltage Vbgr by the voltage dividing ratio r0 to generate the reference voltage Vref. In the circuit of FIG. 1, both the first reference resistors R0a and R0b of the reference voltage dividing resistor pair 14 are configured to be trimmed. The voltage dividing ratio r0 is adjusted by trimming the first reference resistor R0a and the second reference resistor R0b, and as a result, the reference voltage Vref is adjusted.

  The comparators CMP1 to CMPn compare the reference voltage Vref with a plurality of divided voltages Vd1 to Vdn generated by the plurality of voltage dividing resistor pairs RP1 to RPn, respectively. The outputs of the comparators CMP1 to CMPn are output to other circuit blocks as comparison signals S1 to Sn indicating the magnitude relationship.

In the circuit of FIG. 1, the divided voltages Vd1 to Vdn are compared with a common reference voltage Vref. Therefore, the threshold voltage Vthi for the i-th input voltage Vini is
Vthi = Vref / ri
It becomes. In the present embodiment, a separate threshold voltage can be set for each input voltage Vin by appropriately setting the voltage division ratio.

  FIG. 2 is a diagram illustrating a configuration example of the comparator in FIG. Each comparator CMP includes a differential pair DP, a current mirror load CM, and a tail transistor TT. The circuit diagram of FIG. 2 shows only the input stage of each comparator CMP, and the amplification stage and the output stage are omitted. The differential pair DP includes a first transistor M1 and a second transistor M2 which are P-channel MOSFETs (Metal Oxide Semiconductor Field Effect Transistors). The divided voltage Vd is input to the gate of the first transistor M1 of the differential pair, and the reference voltage Vref is applied to the gate of the second transistor M2. A current mirror load CM is connected to the differential pair DP. The current mirror load CM is connected to a third transistor M3 and a fourth transistor M4, which are N-channel MOSFETs. A tail transistor TT is connected to the differential pair DP. The tail transistors TT1 to TTn are current mirror connected to the reference tail transistor TT0. The constant current source 2 is connected to the reference tail transistor TT0. The tail transistor TT generates a tail current proportional to the current flowing through the reference tail transistor TT0.

  The configuration of each comparator CMP is not limited to that shown in FIG. 2, and various types of comparators CMP can be used. For example, it may be composed of a bipolar transistor, or the differential pair may be composed of an N channel MOSFET.

  The voltage comparison circuit 100 according to the present embodiment is integrated on a single semiconductor substrate and has a feature in its layout. FIG. 3 is a layout diagram of the semiconductor substrate 200 on which the voltage comparison circuit 100 of FIG. 1 is formed. On the semiconductor substrate 200, the wiring is laid in the first direction x and the second direction y.

In the present embodiment, the plurality of differential pairs DP <b> 1 to DPn provided in the input stages of the plurality of comparators CMP <b> 1 to CMPn are arranged adjacent to each other in the second region 22 of the semiconductor substrate 200.
With this arrangement, the characteristics of the plurality of comparators CMP1 to CMPn, in particular, the input offset voltage can be made uniform.

  Further, the plurality of current mirror loads CM <b> 1 to CMn provided in the current paths of the respective differential pairs DP <b> 1 to DPn are arranged so as to be adjacent to the third region 24 of the semiconductor substrate 200.

As shown in FIG. 3, the plurality of differential pairs DP1 to DPn and the plurality of current mirror loads CM1 to CMn are arranged adjacent to each other in the first direction x of the semiconductor substrate. The i-th (i is a natural number) differential pair among the plurality of differential pairs DP1 to DPn and the corresponding i-th current mirror load CMi are arranged adjacent to each other in the second direction y.
With this arrangement, since the elements in the same comparator CMP are arranged in the second direction y, wiring becomes easy.

  If the comparator CMP is configured to include a resistor instead of the current mirror load CM, the resistor CMP may be disposed adjacent to the current mirror load CM. That is, the i-th (i is a natural number) differential pair DPi and the corresponding i-th load resistance pair may be arranged adjacent to each other in the second direction y.

  Further, as shown in FIG. 3, the plurality of tail transistors TT <b> 1 to TTn and the reference tail transistor TT <b> 0 may be arranged adjacent to each other in the first region 20. At this time, the reference tail transistor TT0 may be arranged in the center. With this arrangement, the characteristics of the tail transistor are uniform, so that the characteristics of the comparator CMP can be made more uniform.

  Note that the i-th (i is a natural number) differential pair DPi and the corresponding i-th tail transistor TTi may be arranged adjacent to each other in the second direction y. In this case, wiring can be laid more efficiently.

  In the present embodiment, each of the arbitrary first resistor Ria and second resistor Rib constituting the plurality of voltage dividing resistor pairs RP1 to RPn is configured by connecting unit resistor elements in series. As shown in FIG. 3, the unit resistance elements are intensively disposed adjacent to the fourth region 30 on the semiconductor substrate 200. The first resistors R1a to Rna and the second resistors R1b to Rnb are configured by pairing.

  Furthermore, in the present embodiment, the first reference resistor R0a and the second reference resistor R0b of the reference voltage dividing resistor pair 14 are also paired with the voltage dividing resistor pairs RP1 to RPn.

A state of pairing in the fourth region 30 is shown at the bottom of FIG. In the fourth region 30, a plurality of unit resistance elements Re are arranged adjacent to each other.
Pairing is based on the following rules:
1. Unit resistance elements Re constituting two resistors belonging to the same voltage dividing resistor pair are adjacent to each other. For example, the unit resistance elements included in the first reference resistor R0a and the second reference resistor R0b of the reference voltage dividing resistor pair RP0 are adjacent to each other. The unit resistance elements included in the first resistor Ria and the second resistor Rib of the i-th voltage dividing resistor pair RPi are adjacent to each other.

2. A plurality of voltage dividing resistor pairs RP0 to RPn are arranged adjacent to each other to form one segment SEG. The order of voltage dividing resistor pairs in the segment is not limited. Further, a plurality of segments SEG generated by this rule are repeatedly arranged adjacent to each other. The number of unit resistive elements in the plurality of segments does not need to match, and may be changed as appropriate so that a desired resistance value can be obtained.

  This rule ensures that all resistors are preferably paired. That is, since the unit resistance elements constituting the resistors in the same voltage dividing resistor pair are paired, the voltage dividing ratio is kept constant. Furthermore, since a plurality of voltage dividing resistor pairs are paired, even when the voltage dividing ratio for each voltage dividing resistor pair RP varies, the relative variation of the voltage dividing ratio is suppressed.

Advantages of the voltage comparison circuit 100 according to the present embodiment will be described.
In a normal semiconductor process, the input offset voltage of the comparators CMP1 to CMPn is raised as one of the characteristics having a large fluctuation amount. According to the conventional design concept, the plurality of comparators CMP1 to CMPn are separately formed in the vicinity of the wiring where the input voltages Vin1 to Vinn to be monitored appear. In this case, the input offset voltage of each of the comparators CMP1 to CMPn changes independently. As a result, the threshold voltages Vth1 to Vthn change even if the reference voltage Vref and the voltage dividing ratios r1 to rn of the voltage dividing resistor pairs RP1 to RPn are slightly changed. For example, when an offset of +100 mV is generated in the i-th comparator CMPi and an offset of −100 mV is generated in the j-th comparator CMPj, the respective threshold voltages Vthi and Vthj are apparently offset by +100 mV and −100 mV. The This offset cannot be compensated only by adjusting the reference voltage Vref. Therefore, it is necessary to provide a mechanism capable of adjusting the voltage dividing ratios r1 to rn for each of the voltage dividing resistance pairs RP1 to RPn.

On the other hand, in the present embodiment, the differential pairs DP1 to DPn of the input stages of the comparators CMP1 to CMPn are arranged in adjacent regions regardless of the position of the wiring where the input voltages Vin1 to Vinn to be monitored appear. ing. As a result, the offset fluctuations of the comparators CMP1 to CMPn can be made uniform.
For example, if an offset of +100 mV occurs in the i-th comparator CMPi, an offset of about +100 mV also occurs in all other comparators CMP. Therefore, the threshold voltages Vth1 to Vthn for all the input voltages Vin1 to Vinn are apparently offset by about +100 mV. In the voltage comparison circuit 100 according to the present embodiment, the offset amount generated in the comparator CMP can be compensated by adjusting the reference voltage Vref by +100 mV.

  The above is the reason why the trimming mechanism is not required for the voltage dividing resistor pairs RP1 to RPn.

  Even if the differential pairs DP1 to DPn of the comparators CMP1 to CMPn are arranged close to each other, the fluctuations of the input offset voltage can be made uniform, but the current mirror loads CM1 to CMn and the tail transistors TT1 to TTn are similarly arranged. By doing so, the input offset voltage can be made more uniform.

In the present embodiment, consideration is given to the layout of the voltage dividing resistor pairs RP1 to RPn and the reference voltage dividing resistor pair RP0.
By pairing the unit resistance elements constituting the resistors in the same voltage dividing resistor pair, fluctuations in the voltage dividing ratio can be suppressed. Further, since the pairing is performed between a plurality of voltage dividing resistor pairs, even when the voltage dividing ratio for each voltage dividing resistor pair RP varies, the relative variation in the voltage dividing ratio is suppressed.
For example, if the partial pressure ratio ri increases by 10% due to process variations, the other partial pressure ratios rj also increase by about 10%. At this time, the voltage dividing ratio r0 of the reference voltage dividing resistor to RP0 should also increase by 10%, so the reference voltage Vref becomes 1.1 times.
Therefore, the threshold voltages Vth1 and Vthn are both Vth1 = Vref × 1.1 / (r1 × 1.1) = Vref / r1
Vthn = Vref × 1.1 / (rn × 1.1) = Vref / rn
Therefore, fluctuations in the respective threshold voltages Vth can be suppressed.

For example, if the partial pressure ratio r1 is increased by 10% due to process variations or the like, the partial pressure ratio rn is also increased by about 10%. At this time, the voltage dividing ratio r0 of the reference voltage dividing resistor to RP0 should also increase by 10%, so the reference voltage Vref becomes 1.1 times.
Therefore, the threshold voltages Vth1 and Vthn are both Vth1 = Vref × 1.1 / (r1 × 1.1) = Vref / r1
Vthn = Vref × 1.1 / (rn × 1.1) = Vref / rn
Therefore, fluctuations in the respective threshold voltages Vth can be suppressed.

  If only the voltage dividing ratio r0 of the reference voltage dividing resistor RP0 changes differently, the first reference resistor R0a and the second reference resistor R0b are trimmed to change the voltage dividing ratios r1 to rn. The partial pressure ratio r0 may be adjusted according to the amount.

  Some processes have very small resistance fluctuations. When such a process is used, the flexibility of the resistor layout is increased, and the threshold voltages Vth1 to Vthn can be set with high accuracy without following the rules described above.

As described above, according to the voltage comparison circuit 100 according to the present embodiment, even when the resistance value and the offset voltage of the comparator vary, the circuit is easily manufactured because only the reference voltage Vref is adjusted.
Furthermore, in the voltage comparison circuit 100 according to the present embodiment, in addition to process variations, it is possible to suppress variations in the characteristics of comparators and resistors due to temperature variations.

FIG. 4 is a block diagram showing a configuration of a power supply device using the voltage comparison circuit 100 of FIG.
The power supply device 300 is mounted on the electronic device 400. The electronic device 400 is, for example, a mobile phone terminal or a PDA, and includes loads such as a processor that operates with different power supply voltages, a liquid crystal backlight, other digital circuits, and analog circuits. In FIG. 4, the plurality of loads are denoted by 310a to 310d.

  The power supply device 300 generates a plurality of voltages V1 to V4. The voltages V1 to V4 are supplied to the loads 310a to 310d as power supply voltages.

  The power supply apparatus 300 includes a voltage comparison circuit 100, a control unit 110, and a plurality of voltage generation units 120a to 120d, and is configured as a power management ID. The voltage generators 120a to 120d are linear regulators and switching regulators, and generate voltages V1 to V4 using battery voltages output from batteries (not shown), respectively.

  The voltage comparison circuit 100 monitors the voltages V1 to V4 generated by the plurality of voltage generation units 120a to 120d and compares them with the corresponding threshold voltages Vth1 to Vth4. That is, the voltages V1 to V4 in FIG. 4 correspond to the input voltages Vin1 to Vin4 in FIG. The comparison result is input to the control unit 110 as signals S1 to S4. The control unit 110 refers to the signals S1 to S4 and executes predetermined processing based on the comparison result of the voltage comparison circuit 100. Examples of the predetermined process include notification of completion of activation of each of the voltage generation units 120a to 120d to a host processor provided outside the power supply apparatus 300. Alternatively, the control unit 110 may start / stop the voltage generation units 120a to 120d in a predetermined order based on the comparison result. Specifically, the activation of another voltage generator may be started when a certain voltage V1 becomes higher than the threshold voltage Vth1.

Thus, the voltage comparison circuit 100 according to the present embodiment can be suitably used for the power supply device 300 that generates a plurality of voltages.
The voltage comparison circuit 100 may monitor a power supply voltage supplied from the outside. In this case, it can function as a UVLO (Under Voltage Lock Out) circuit.

  Although the present invention has been described based on the embodiments, the embodiments merely illustrate the principle and application of the present invention, and the embodiments are intended to include the idea of the present invention defined in the claims. Many modifications and changes in arrangement are possible within the range not leaving.

It is a circuit diagram which shows the structure of the voltage comparison circuit which concerns on embodiment. It is a figure which shows the structural example of the comparator of FIG. FIG. 2 is a layout diagram of a semiconductor substrate on which the voltage comparison circuit of FIG. 1 is formed. It is a block diagram which shows the structure of the power supply device using the voltage comparison circuit of FIG.

Explanation of symbols

  100 voltage comparison circuit, RP voltage dividing resistor pair, CMP comparator, DP differential pair, CM current mirror load, TT tail transistor, P input terminal, Ra first resistor, Rb second resistor, S comparison signal, 10 reference voltage source , 12 reference voltage circuit, 14 reference voltage dividing resistor pair, R0a first reference resistor, R0b second reference resistor, 20 first region, 22 second region, 24 third region, 30 fourth region, 110 control unit, 120 Voltage generator, 300 power supply, 310 load, 400 electronic equipment.

Claims (11)

A voltage comparison circuit that compares a plurality of input voltages with a threshold voltage set for each to determine a magnitude relationship,
A plurality of voltage dividing resistor pairs that divide the plurality of input voltages by a voltage dividing ratio set to each of the plurality of voltage dividing resistors and generate a plurality of divided voltages;
A reference voltage source for generating an adjustable reference voltage;
A plurality of comparators respectively comparing the reference voltage with a plurality of divided voltages generated by the plurality of voltage dividing resistor pairs;
With
A voltage comparison circuit, wherein a plurality of differential pairs respectively provided at input stages of the plurality of comparators are arranged adjacent to each other on a semiconductor substrate.   2. The voltage comparison circuit according to claim 1, wherein a plurality of current mirror loads provided in current paths of the respective differential pairs are arranged adjacent to each other on a semiconductor substrate. The plurality of differential pairs are disposed adjacent to the first direction of the semiconductor substrate, and the plurality of current mirror loads are disposed adjacent to the first direction of the semiconductor substrate;
An i-th (i is a natural number) differential pair of the plurality of differential pairs and a corresponding i-th current mirror load are adjacent to each other in a second direction perpendicular to the first direction. The voltage comparison circuit according to claim 2, wherein the voltage comparison circuit is arranged.   3. The voltage comparison circuit according to claim 2, wherein a plurality of resistance load pairs provided in place of the plurality of current mirror loads are arranged adjacent to each other on a semiconductor substrate. The plurality of differential pairs are disposed adjacent to the first direction of the semiconductor substrate, and the plurality of load resistance pairs are disposed adjacent to the first direction of the semiconductor substrate,
An i-th (i is a natural number) differential pair of the plurality of differential pairs and a corresponding i-th load resistance pair are adjacent to each other in a second direction perpendicular to the first direction. The voltage comparison circuit according to claim 4, wherein the voltage comparison circuit is arranged.   The voltage comparison circuit according to claim 1, wherein a plurality of tail transistors that cause tail currents to flow through the plurality of differential pairs are arranged adjacent to each other on a semiconductor substrate. The plurality of differential pairs are disposed adjacent to the first direction of the semiconductor substrate, and the plurality of tail transistors are disposed adjacent to the first direction of the semiconductor substrate;
An i-th (i is a natural number) differential pair of the plurality of differential pairs and a corresponding i-th tail transistor are adjacent to each other in a second direction perpendicular to the first direction. The voltage comparison circuit according to claim 6, wherein the voltage comparison circuit is arranged. Each of the plurality of voltage dividing resistor pairs includes first and second resistors configured by connecting unit resistor elements in series,
2. The voltage comparison circuit according to claim 1, wherein the unit resistance elements are arranged in a concentrated manner in a predetermined region on a semiconductor substrate, and the plurality of voltage dividing resistor pairs are paired. The reference voltage source is
A reference voltage circuit for generating a predetermined constant voltage;
A reference voltage dividing resistor pair that divides the constant voltage and generates the reference voltage;
The voltage comparison circuit according to claim 1, wherein at least one of the reference voltage dividing resistor pair is configured to be trimmed. Each of the plurality of voltage dividing resistor pairs includes first and second resistors configured by connecting unit resistor elements in series,
The reference voltage source is
A reference voltage circuit for generating a predetermined constant voltage;
A reference voltage dividing resistor pair that divides the constant voltage and generates the reference voltage;
Including
The reference voltage dividing resistor pair includes first and second reference resistors configured by connecting unit resistor elements in series, at least one of which is configured to be capable of trimming,
2. The unit resistance element is configured by concentrating and arranging the unit resistor elements in a predetermined region on a semiconductor substrate and pairing the plurality of voltage dividing resistor pairs and the reference voltage dividing resistor pair. The voltage comparison circuit described. A power supply circuit for generating a plurality of voltages;
The voltage comparison circuit according to any one of claims 1 to 10, wherein a plurality of voltages output from the power supply circuit are compared with a plurality of threshold voltages.
A control unit that executes predetermined processing based on a comparison result of the voltage comparison circuit;
A power management circuit comprising:

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