JPH04156107A - Comparator circuit - Google Patents

Abstract

PURPOSE:To automatically adjust the offset of a comparator for the purpose of equalizing response times of comparators by correcting unmatching of the response characteristic of the comparator and performing the comparing operation in this state. CONSTITUTION:Since the same signal as the signal inputted to a comparator 1 is inputted to comparators 2 and 3 with different polarities to obtain response signals, response signals of comparators 2 and 3 approximately correspond to response times tPLN and tPML of the comparator 1 respectively. A decoder 5 checks and analyzes them to detect response times tPLN and tPML, and integral values as DC voltage values corresponding to response times are obtained from this detection output by an integrator 6, and an input voltage to an offset adjustment terminal is obtained by an affset adjusting circuit 7. Since the input signal to the comparator 1 is inputted through an analog delay circuit 4, offset adjustment is set and the comparator 1 performs the comparison in this state. Thus, adjustment to equalize the response times is automatically performed.

Description

[Detailed description of the invention] [Table of contents] Overview Industrial field of application Prior art (Figures 5 and 6) Problems to be solved by the invention Means for solving the problems (Figure 1) Working examples (Figures 2 to 4) Effects of the invention [Summary] The purpose of the present invention is to automatically adjust the offset adjustment i of the comparator in order to equalize the response time (LPLH and tP) of the comparator (IL) and the comparator circuit. , compares the input voltage with an arbitrary voltage value and outputs it.

The inhalator circuit includes a delay means for delaying a signal to the comparator by a predetermined time, a comparator for compensation provided on the same semiconductor substrate as the comparator, and a comparator for correction. a decoder for receiving the output of the decoder and analyzing its response characteristics, a one-minute means for converting the output of the decoder into a DC voltage, and an offset adjusting means for obtaining an output for offset adjustment of the comparator from the output of the integrating means. In addition, the comparison operation is performed in a state in which an unitch in the response characteristic of the comparator is corrected.

[Industrial application field]

The present invention relates to a comparator circuit, and particularly to a comparator circuit used for reading digital signals magnetically recorded on a magnetic disk device or the like.

When reading signals recorded on a magnetic recording medium such as a magnetic disk, the reading control is performed using a magnetic head, etc.
The signal to be processed is in an analog state, and this analog
Digital signals are generated by comparing human signals with specific voltage values.
Make it. This analog input signal and specific voltage value are
A comparator is used as a comparator for comparison.

As is well known, a comparator compares the voltage input manually to two input voltages 1, detects when the voltage exceeds a specific voltage, and outputs it, or converts the voltage input to two input terminals into a differential voltage. As input, detect the point in time when the difference becomes positive or negative. Figure 5 shows the operation of this comparator. In FIG. 5, a comparator 51 detects the point in time when the input VHH1 on the slave voltage side becomes higher than the Ars potential on the other one voltage side, and 52 indicates the voltage between the input VIN+ on the slave voltage side and the voltage on the one voltage side. This is to detect the point in time when the differential component of 1NZ becomes positive or negative. If a sine wave is used as a representative input waveform, an output 54 is obtained for an input waveform 53 in either case.

It takes a response time depending on the characteristics of the comparator until the time when the input 53 changes from negative to positive or until the time when the input 53 changes from positive to negative is detected. In this case, as shown in the diagram, the response time tPLH for a change from the negative side to the positive side and the response time t□1 for a change from the positive side to the negative side are not exactly the same, and a slight difference occurs. become.

In recent years, there has been an increasing demand for faster operation of magnetic disks, etc., and there is a demand for faster response characteristics and equalization of response times of this comparator. In response to the demand for higher speeds, considerable improvements have been made through improvements in semiconductor processes, but as the speeds increase, the response time t PLt
+ and the response time tPAIL are beginning to become noticeable, and there is a growing demand for making each response time the same.

[Conventional technology]

In order to make the response times the same, conventionally, as shown in FIG. 6, a potential for offset adjustment is applied to the offset adjustment voltages X and Y using a variable resistor 60 and a power supply 6I. Each response time is made the same by adjusting the variable resistor 60 while observing the waveform with an oscilloscope or the like.

FIG. 4 is a detailed diagram of the offset adjustment voltage section of the comparator. In a normal converter, the input voltage is provided on the input side of the differential amplifier, and the offset adjustment voltage
This is achieved by providing Y as shown in the figure and adjusting the relationship between Vllt and IC of each transistor of the differential amplifier in a well-balanced manner.

[Problem to be solved by the invention]

In the conventional example described above, the offset adjustment is done manually, which takes time, and also requires readjustment when the comparator is replaced with another sample. There is. Moreover, if the input amplitude differs from that at the time of adjustment, the overdrive amount of the comparator will change, and the response time crt, l=response time t
This poses the problem of not being able to maintain the PNL relationship.

The present invention has been made in view of these points, and it is an object of the present invention to provide a comparator circuit that can automatically adjust the response time LPLH to the response times LP and 1L.

[Means to solve the problem]

FIG. 1 is a diagram for explaining the present invention in detail. 1st
In the figure, 2.3 is a comparator, which has a monolithic structure and is made adjacent to the same semiconductor substrate. 4 is an analog delay circuit; 5 is a decoder;
6 is an integrator, and 7 is an offset adjustment circuit. Comparators 1, 2 and 3 have the same inputs VIN+ and V
(H□ is connected, but the comparator 2.
are connected in such a way that they are input in an inverse relationship.

D: I-9”5 is the output ■2 from comparator 2.3,
■, to analyze the response characteristics of comparator 1 by investigating the response time Lp and response time t PNL
Figure out which one is longer. 6 is decoder 5
7 is an offset adjustment circuit that generates an adjustment voltage to be applied to the offset voltage according to the output of the integrator 6. be. The analog delay circuit 4 is also provided to ensure that an input signal is supplied to the comparator 1, in particular the comparator 1 offset-adjusted by the voltage from the offset adjustment circuit.

[Effect]

Since the comparators 1 and 2.3 are constituted by monolithic integrated circuits, the response characteristics of each comparator tend to be approximately equal. Therefore, by examining the characteristics of comparator 2.3, the response characteristics of comparator 1 can be known almost accurately.

Since the same signal as that input to comparator l is input to comparators 2.3 with different polarities to obtain its response signal, the response signal of comparator 2.3 is the response time of comparator l, respectively. This means that a signal is output approximately corresponding to LAALI1 and response time tPML. Therefore, we investigated this using decoder 5.
It is analyzed to detect which of the response time tPLH and the response time tPLH is longer. This output is integrated by an integrator 6 to obtain an integral value that becomes a DC voltage value corresponding to the response time, and an input voltage to an offset adjustment voltage is obtained by an offset adjustment circuit 7. Since the input signal to the comparator 1 is inputted via the analog delay circuit 4, the comparator 1 performs the comparison with the offset adjustment set. Therefore, the comparator 1 can perform the comparison operation while maintaining the relationship of response time tPLII - response time tPML.

〔Example〕

FIG. 2 shows an embodiment of the invention. In Figure 2, the first
The same numbers are assigned to the same parts as in the principle part of the figure, so a detailed explanation of those parts will be omitted.

In this embodiment, the decoder 5 is connected to an AND gate 8 and a NOR gate.
The integrator 6 is composed of a diode, a resistor, and a capacitor, and the offset adjustment circuit 7 is composed of two FETs l0°11 and a bias supply power supply 1.
It is composed of 2.

This operation will be explained with reference to FIG. Figure 3 shows two examples based on differences in the response characteristics of the comparators, but the basics of their operation are the same, and here we will use Figure 3 (A
), we mainly explain the case where there is a relationship L FLII < t FM between the response time t2゜ for a change from the negative side to the positive side and the response time t□ for a change from the positive side to the negative side. do.

In FIG. 2, the signal VIN is applied to voltages 11 and 12, respectively.
When I and VHH2 are connected, VIN+ is applied to the child voltage of comparator 2, and V and 1 are applied to one voltage, so that comparator 2 has a differential input (V+) shown in FIG. 3(A).
□-VINE) will be input, and a signal of opposite polarity = (VINIVINz) will be input to the comparator 3.

As mentioned above, the response characteristic of comparator 2.3 is tPL
Since H<L PML, this comparator 2 outputs the comparison result as shown by vz in FIG. 3(A).

On the other hand, the comparator 3 outputs a comparison result as shown in (2) in FIG. 3(A).

When the outputs V, , V, of the comparator 2.3 are input to the decoder 5, the output of the AND gate 8 is a pulse-like output vl in which both V and V become rl only when IJ.
It becomes l. In NOR gate 9, ■2 and ■ are both "0"
Since the output of the NOR gate 9 becomes "l" when V, all outputs of the NOR gate 9 become "0" as shown in V.

In the above case, the response characteristic of comparator 2.3 is t, □〈
The operation has been explained assuming that tP and L, but conversely, when the output 1 of the AND gate 8 in the decoder 5 outputs some kind of pulse signal, the response characteristic of the comparator 2.3 is L PLH<L This means that it is PHL. Then, the width of the pulse of output ■8 is tPLH and t□
This shows the difference in magnitude of 1.

As stated at the beginning, since comparators 1, 2, and 3 are made of a monolithic structure on the same semiconductor substrate, it can be considered that the response characteristics of comparators 1, 2, and 3 are all approximately equal. Therefore, the results of the investigation and analysis of comparator 2.3 can be applied to comparator 1.

The pulse of output (1) is integrated by an integrator 6 to obtain a voltage v1' (see V,' in FIG. 3(A)) proportional to the pulse width. Furthermore, this is connected to the FET of the offset adjustment circuit 7.
This adjusts the voltage of the bias power supply 12 according to the difference in magnitude between t PLH and t FIL and applies it to the offset adjustment voltage X of the comparator 1 as an offset adjustment signal.

Since the input signal to the comparator 1 is input manually via the analog delay circuit 4, it is input with the voltage applied for the offset adjustment described above, and the comparison operation is performed with the offset correction set. will be carried out.

The response characteristic of comparator 2.3 is L PLH> t□1
In this case, as shown in FIG. 3 (CB), the output (2) of the NOR gate 9 outputs a pulse signal corresponding to the difference between t PLjl and t FIL. In this case as well, this pulse signal is integrated by the analyzer 6 and converted into a DC voltage according to the above-mentioned difference, which is applied to the gate of FET II. by this,
The voltage of the bias power supply 12 is adjusted according to the difference in magnitude between L PLH and t PIIL, and then applied to the offset adjustment voltage Y of the comparator 1 as an offset adjustment signal.

〔Effect of the invention〕

As explained above, according to the present invention, the unmatched response characteristics of the comparator (t FLII≠L
P, IL) can be accurately corrected. Therefore, it greatly contributes to improving the performance of magnetic disk devices.

[Brief explanation of the drawing]

FIG. 1 is a principle block diagram for explaining the present invention in detail; FIG. 2 is a diagram showing an embodiment of the present invention; FIG. 3 is an operational explanatory diagram for explaining the present invention in detail; 5 is a diagram showing details of the comparator offset adjustment voltage section, FIG. 5 is a diagram showing the response characteristics of the comparator, and FIG. 6 is a diagram showing a conventional method for adjusting the comparator response characteristics. 1.2.3 - Comparator 4 - Analog delay circuit 5 - Decoder 6 - Integrator 7 - Offset adjustment circuit Input difference (Wmt-Vy2) Fig. 5 Fig. 6

Claims (2)

[Claims] (1) In a comparator circuit that compares an input voltage with an arbitrary voltage value and outputs the result, a delay means (4) that delays the input signal to the comparator (1) by a predetermined time, and a semiconductor that is the same as the comparator (1) are used. Comparators (2) and (3) for correction provided on the board; a decoder (5) that receives the outputs of the comparators (2) and (3) for correction and analyzes their response characteristics; and the decoder ( an integrating means (6) for converting the output of the integrating means (5) into a DC voltage; and an integrating means (6) for converting the output of the integrating means (6) to the comparator (1).
offset adjustment means (7) for obtaining an offset adjustment output of
), the comparator circuit is characterized in that it performs a comparison operation in a state where an unmatch in response characteristics of the comparator is corrected. (2) The comparator circuit according to claim 1, wherein the decoder (5) is constructed of an AND gate and a NOR gate.