JPS61189472A - Testing method for integrating circuit - Google Patents
Testing method for integrating circuitInfo
- Publication number
- JPS61189472A JPS61189472A JP2965585A JP2965585A JPS61189472A JP S61189472 A JPS61189472 A JP S61189472A JP 2965585 A JP2965585 A JP 2965585A JP 2965585 A JP2965585 A JP 2965585A JP S61189472 A JPS61189472 A JP S61189472A
- Authority
- JP
- Japan
- Prior art keywords
- frequency
- tester
- frequency divider
- oscillation
- signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/316—Testing of analog circuits
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/24—Marginal checking or other specified testing methods not covered by G06F11/26, e.g. race tests
Landscapes
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Computer Hardware Design (AREA)
- Quality & Reliability (AREA)
- Tests Of Electronic Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は集積回路の試験方法に関し、特に高周波発振回
路を必要とする集積回路の試験方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for testing integrated circuits, and particularly to a method for testing integrated circuits that require a high frequency oscillation circuit.
従来、この種の試験法は集積回路専用テスターの動作速
度よりも、被測定用集積回路の動作速度（発振周波数が
高い）が速い究め一般には手動により測定を行なってい
る。Conventionally, in this type of testing method, the operating speed of the integrated circuit under test (having a higher oscillation frequency) is faster than the operating speed of a tester dedicated to integrated circuits, and measurements are generally performed manually.
上述し几従来の集積回路の試験法は手動方式を採用して
いるため集積回路の試験に於いて発振特性は手動で、発
振特性以外は、自動テスターで行なうことになり、試験
の処理時間が一般の集積回路に比べて倍以上かかるとい
う欠点がある。As mentioned above, the conventional integrated circuit testing method uses a manual method, so when testing integrated circuits, the oscillation characteristics are tested manually, and everything other than the oscillation characteristics is tested using an automatic tester, which reduces the processing time of the test. The drawback is that it takes more than twice as long as a general integrated circuit.
本発明の集積回路の試験法は被測定用集積回路と集積回
路用テスター間に分周器を挿入し、この分周器出力の周
期から発振周波数を検出するものである。The integrated circuit testing method of the present invention involves inserting a frequency divider between the integrated circuit under test and the integrated circuit tester, and detecting the oscillation frequency from the period of the output of the frequency divider.
次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図は本発明の一実施例のシステム回路図である。一
般的に集積回路専用テスター４（以下テスターと称す）
で集積回路ｌ（以下ｔＣと称す）の電気的特性を測定す
るときは、テスター４からの命令信号ｄがＥＣ１の入力
端子に入力されＩＣ１をプログラマブルに動作させるこ
とにより、その内容をＩＣ１の出力端子に出力させ、そ
の情報ｅをテスター４に入力し、あらかじめ用意されて
いるテスター４内の期待値と照合し、測定データの判断
を行なう。本発明では、前記測定以外にＩＣ１の発振周
波数を測定する几めに外部に分周器６を設け、ＩＣの発
振信号ａが２ＮＡＮＤゲート５の一方の入力に入力され
、もう−万の入力は、テスター４から送られてぐる分周
器６の初期設定信号すとして入力される。分周器６は発
振信号をクロックとして分周が行なわれ、分周器６の出
力Ｑから信号が送信されこの信号をテスター４が受けて
期待値と照合して発振周波数の良否の判断を行なう。FIG. 1 is a system circuit diagram of an embodiment of the present invention. Generally, tester 4 for integrated circuits (hereinafter referred to as tester)
When measuring the electrical characteristics of an integrated circuit l (hereinafter referred to as tC), the command signal d from the tester 4 is input to the input terminal of EC1, and by operating IC1 in a programmable manner, the contents are outputted from IC1. The information e is outputted to the terminal, inputted into the tester 4, and compared with the expected value in the tester 4 prepared in advance to judge the measured data. In the present invention, a frequency divider 6 is provided externally to measure the oscillation frequency of the IC 1 in addition to the above-mentioned measurement, and the oscillation signal a of the IC is input to one input of the 2NAND gate 5, and the input of the other -10,000 is , is sent from the tester 4 and input as the initial setting signal of the frequency divider 6. The frequency divider 6 performs frequency division using the oscillation signal as a clock, and a signal is transmitted from the output Q of the frequency divider 6, and the tester 4 receives this signal and compares it with the expected value to judge whether the oscillation frequency is good or bad. .
第２図は具体的な信号波形のタイミングチャートである
。ａはＩＣ１の発振信号であり、テスター４からの信号
ｂＨ初期設定するため最初は低電位状態になっており、
このとき、２ＮＡＮＤ ゲー）５ｉｄ閉じ、分周器６は
リセット状態にある。ここでテスター４の命令により信
号すが立上る（低電位→高電位）と、２ＮＡＮ１）ゲー
ト５及び分周器６の入力が開く九め、発振信号ａを分周
器６に入力できる状態となる。分周器６の出力Ｑは発振
信号ａを入力してから、ｎ分周した後信号Ｃは立上る（
ここで発振周波数信号と分周器とが同期とれｔことにな
る）。この時点からテスター４の分周器６の周期時間の
測定が開始され、次に立下る（高電位→低電位）まで測
定される。測定が終ｒすると、信号すは豆下り分周器６
がリセット状態になる。尚テスター４での判断は分周器
６をバイナリイ方式にし九場合、次の様に計算される。FIG. 2 is a timing chart of specific signal waveforms. a is the oscillation signal of IC1, and signal bH from tester 4 is initially in a low potential state to initialize,
At this time, the 2NAND gate 5id is closed and the frequency divider 6 is in a reset state. Here, when the signal rises (from low potential to high potential) according to the command from tester 4, the inputs of 2NAN1) gate 5 and frequency divider 6 open, and the oscillation signal a can be input to frequency divider 6. Become. The output Q of the frequency divider 6 inputs the oscillation signal a, and after dividing the frequency by n, the signal C rises (
At this point, the oscillation frequency signal and the frequency divider are synchronized. Measurement of the cycle time of the frequency divider 6 of the tester 4 is started from this point, and measurement is continued until the next fall (from high potential to low potential). When the measurement is completed, the signal is output to the downstream frequency divider 6.
goes into reset state. Note that the determination by the tester 4 is calculated as follows when the frequency divider 6 is set to the binary system.
ｆｏ：発振周波数、Ｔｏ：発振周期
Ｔ：測定周期、ｎ：分局段数
〔発明の効果〕
以上説明し友ように本発明は、外部に分周期を設定する
ことによりテスターの動作周波数より高い周波数源をも
つｆｃＩＣを自動的に測定することができる効果がある
。fo: oscillation frequency, To: oscillation period T: measurement period, n: number of division stages [Effects of the invention] As explained above, the present invention provides a frequency source higher than the operating frequency of the tester by setting an external division period. This has the effect of automatically measuring fcIC.
第１図は本発明の一実施例によるテストシステムの回路
図、第２図は口略図内信号のタイミングチャートである
。
１・・・・・・被測定集積回路、２・・・・・・発振イ
ノバータ、３・・・・・・水晶撮動子、４・・自・・集
積回路専用テスター、５・・・・・・２ＮＡＮＤゲート
、６・・川・分周期、ａ・・・・・・発振信号、ｂ・・
・・・・分周器の初期設定信号、Ｃ・・・・・・分周器
出力信号、ｄ・・・・・・集積回路専用テスターから被
測定集積回路への命令信号、ｅ・・・・・・被測定集積
回路から集積回路専用テスターへのデータ信号。
／９４むり゛チャート
茅２回FIG. 1 is a circuit diagram of a test system according to an embodiment of the present invention, and FIG. 2 is a timing chart of signals in the diagram. DESCRIPTION OF SYMBOLS 1... Integrated circuit under test, 2... Oscillation inverter, 3... Crystal sensor, 4... Self... Integrated circuit dedicated tester, 5...・・2NAND gate, 6・・river division period, a・・oscillation signal, b・・
... Frequency divider initial setting signal, C... Frequency divider output signal, d... Command signal from the integrated circuit dedicated tester to the integrated circuit under test, e... ...Data signal from the integrated circuit under test to the integrated circuit dedicated tester. /94 Muri゛Chart Kaya 2 times
Claims (1)
周器の分周出力を集積回路用テスターに入力し、該テス
ターより前記分周器の分周出力の周期を測定する事によ
り被測定用集積回路の発振周波数を測定することを特徴
とする集積回路の試験方法。Divide the oscillation output of the integrated circuit under test by a frequency divider, input the divided output of the frequency divider to an integrated circuit tester, and measure the period of the divided output of the frequency divider using the tester. A method for testing an integrated circuit, comprising: measuring the oscillation frequency of an integrated circuit under test.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2965585A JPS61189472A (en) | 1985-02-18 | 1985-02-18 | Testing method for integrating circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2965585A JPS61189472A (en) | 1985-02-18 | 1985-02-18 | Testing method for integrating circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61189472A true JPS61189472A (en) | 1986-08-23 |
Family
ID=12282125
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2965585A Pending JPS61189472A (en) | 1985-02-18 | 1985-02-18 | Testing method for integrating circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61189472A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0396272A2 (en) * | 1989-05-02 | 1990-11-07 | Kabushiki Kaisha Toshiba | IC device including test circuit |
| US5260931A (en) * | 1990-10-02 | 1993-11-09 | Tdk Corporation | Disk cartridge with improved transmission shutter mechanism |
-
1985
- 1985-02-18 JP JP2965585A patent/JPS61189472A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0396272A2 (en) * | 1989-05-02 | 1990-11-07 | Kabushiki Kaisha Toshiba | IC device including test circuit |
| US5260931A (en) * | 1990-10-02 | 1993-11-09 | Tdk Corporation | Disk cartridge with improved transmission shutter mechanism |
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