JPH1152015A - Test circuit for high-speed semiconductor integrated circuit apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable the logic operation and the timing operation of a semiconductor integrated circuit apparatus driven at high speed with the use of a low- speed tester. SOLUTION: The high-speed clock signal of a semiconductor integrated circuit apparatus 101 driven at high speed, and a data signal output subsequent to the high-speed clock signal are AND operated at a first AND circuit 111, and the obtained AND output is counted by a first counter 112. The AND output and an AND output delayed from the AND output are AND operated at a second AND circuit 114, and the thus-obtained AND output is counted by a second counter 115. The counted values of the first and second counters are compared with each other by a coincidence detection circuit 116. When the counted values coincide, a timing normal signal is output. A low-speed tester carries out a timing test to the semiconductor integrated circuit apparatus with this timing normal signal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a test circuit for checking the operation of a semiconductor integrated circuit device, and more particularly to a circuit for testing a high-speed semiconductor integrated circuit device using a low-speed tester.

[0002]

2. Description of the Related Art In recent years, the speed of a semiconductor integrated circuit device represented by an MPU has been increased, and accordingly, a human output interface circuit of a semiconductor integrated circuit has been required to operate at a high speed. For example, the interface system proposed by Rambus in the United States is a clock synchronous operation of 250 MHz, and data input / output is performed in response to both rising and falling edges of the clock. The double data input / output operation of 500 Mbytes / sec is realized. In this data input / output method, the relationship between the clock signal and the data signal is 90 ° out of phase, and the timing of the falling edge of the clock is located at the center between the data waveform change timings. . This is to ensure a sufficient setup time / hold time margin of the circuit receiving the data signal.

Since a high-speed tester capable of testing such a high-speed interface circuit is expensive, the introduction of such a high-speed tester raises the test cost. It is hoped that this test will be feasible. For this reason, a self-test circuit was built in a part of the high-speed interface circuit in a part of the high-speed circuit, and the test was executed by the self-test circuit, thereby realizing a test of the high-speed circuit by a low-speed tester. Things have been suggested. FIG. 7 shows an example of a test method for a high-speed circuit using such a low-speed tester. In FIG. 7, reference numeral 701 denotes a semiconductor integrated circuit device to be inspected having a high-speed interface circuit 702 on a chip. In this high-speed interface circuit 702,
A BIST (Bulot In Self Test) circuit 703 is built in, receives a clock from a high-speed clock generation circuit 710 mounted on a test board, and performs self-diagnosis of input / output operations. The high-speed interface circuit 702 includes a data output circuit including a flip-flop 705 and a buffer 707, and operates in synchronization with a clock generated by a 90 ° phase modulation circuit 706. A clock (Cloc) is generated by the phase modulation circuit 706.
k) The timing margin between the signal and the data (Data) signal is maintained.

In this method, when a low-speed tester executes BIST, a low-speed tester driver 712 transmits a BIST
The start signal of T is input. Then, the clock generation circuit 710
When the BIST circuit 703 operates with the clock supplied from the
“1” is output as the G signal. When the signal is received by the comparator 711 of the tester, it is determined that the semiconductor integrated circuit device (701) to be tested is a non-defective product. As described above, in this type of test circuit, a high-speed clock is generated by the clock generation circuit 710 independent of the low-speed tester and the BIST test is performed, so that a high-speed test using the low-speed tester can be realized.

[0005]

However, this B
The IST circuit has only a check function of only the logical operation,
No timing check is performed. That is, as shown in the time chart of each signal in FIG. 8, the Clock signal and the Data signal have a phase shift of 90 °, that is, 1/4.
A timing shift corresponding to a cycle is intentionally generated. Also,
In the BIST, the test is completed after a certain period of time after the BISTSTART signal becomes high level,
The test result is output to the LAG signal. At this time, BI
Although the logical operation can be confirmed by ST, as described above, the high-speed clock used for the BIST operates independently of the low-speed tester, and the low-speed tester operates at a low speed. Since it is impossible to perform measurement with the measurement accuracy described above, the timing check of the phase difference of the Data signal cannot be performed, and a reliable test cannot be performed. For example, a low-speed tester having a measurement error of 1 nsec cannot measure a timing of 500 psec.

SUMMARY OF THE INVENTION An object of the present invention is to provide a test circuit capable of inspecting the timing of high-speed operation, which has not been possible with a low-speed tester.

[0007]

According to the present invention, there is provided a clock signal for driving a high-speed semiconductor integrated circuit device to be measured, and at a different timing with respect to the clock signal when the high-speed semiconductor integrated circuit device is driven. A first AND circuit for performing an AND operation with the output data signal; an output signal of the first AND circuit; and a signal obtained by delaying the output signal of the first AND circuit by a predetermined amount. A second AND circuit for calculating an AND, a first counting circuit for counting the output of the first AND circuit, a second counting circuit for counting the output of the second AND circuit, The first counting circuit and the second counting circuit
And a match detection circuit that compares the count values of the counter circuits and outputs a normal timing signal when the count values match.

The present invention is also directed to a clock signal for driving a high-speed semiconductor integrated circuit device to be measured, and data output at a different timing from the clock signal when the high-speed semiconductor integrated circuit device is driven. A first AND circuit for obtaining a logical AND with a signal; an output signal of the first AND circuit; and a signal obtained by delaying the output signal of the first AND circuit by a predetermined amount. A second AND circuit, a first counting circuit for counting the output of the first AND circuit, and a second counting circuit for counting the output of the second AND circuit
A first match detection circuit that compares respective count values of the first count circuit and the second count circuit and outputs a match signal when the count values match each other; A third AND circuit for obtaining a logical product of the inverted signal of the clock signal; an output signal of the third logical product circuit;
A fourth AND circuit for performing an AND operation with a signal obtained by delaying the output signal of the AND circuit by a predetermined amount; a third counting circuit for counting the output of the third AND circuit; A fourth counting circuit that counts the output of the AND circuit, and a count value that compares each count value of the third count circuit and the count value of the fourth count circuit, and outputs a match signal when both match. 2 match detection circuits, and a fifth AND circuit that outputs a timing normal signal when a match signal is output from each of the first match detection circuit and the second match detection circuit.

The self-diagnosis circuit provided in the semiconductor integrated circuit device can test whether the logical operation is operating normally, perform a logical operation on the clock signal and the data signal, and count the output thereof. By determining the coincidence of the count values, it is possible to test whether the semiconductor integrated circuit device is operating at the correct timing, and it is possible to perform these tests with a low-speed tester.

[0010]

Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a circuit diagram of a first embodiment of the present invention. In FIG. 1, reference numeral 101 denotes a semiconductor integrated circuit device to be inspected having a high-speed interface circuit 102 on a chip, and a BIST circuit 103 is built in the high-speed interface circuit 102. The BIST circuit 103 receives a clock from the high-speed clock generation circuit 110 mounted on the test board, and performs a self-diagnosis of the input / output operation. The high-speed interface circuit 102 includes a data output circuit including a flip-flop 105 and a buffer 107.
It operates in synchronization with the clock generated by the 90 ° phase modulation circuit 106. The phase modulation circuit 106
The timing margin between the ock signal and the Data signal is maintained. The above configuration is the same as the conventional configuration shown in FIG. 7, but here, a logic circuit that receives the Clock signal and the Data signal is configured on a test board on which the high-speed clock generation circuit is mounted. I have.

The logic circuit performs a logical AND operation on the Clock signal and the Data signal having different phases by 90 ° as described above, and observes the pulse width to test whether or not the phase difference is sufficient. Have been. That is, due to the logical product circuit 111, Cl having different phases is used.
The logical product of the ock signal and the Data signal is obtained, and the number of pulses of the waveform is counted by the counter 112. Further, the output of the AND circuit 111 and the AND circuit 111
Is ANDed by a logical product circuit 114 with a signal obtained by delaying the output of the logical product
The number of pulses of the 14 output waveform is counted by the counter 115. Then, the coincidence detection circuit 116 outputs the counter 1
12 is compared with the count number of the counter 115, and when they match, a high level is output, and when they do not match, a low level is output. The definition of the output level of the match detection circuit may be reversed depending on whether or not the match is made.
Note that it is necessary to input a reset signal from the tester driver 120 to the counters 112 and 115, perform a reset immediately before starting the test for timing confirmation, and initialize the count number.

In this test circuit, a low-speed tester uses a BI
When executing ST, a BIST start signal is input from the driver 112 of the low-speed tester. Then, the BIST circuit 103 operates according to the Clock signal supplied from the clock generation circuit 110, and if the test ends normally, B
“1” is output as the ISTFLAG signal. When the comparator 711 of the low-speed tester receives the signal, it is determined that the semiconductor integrated circuit device 101 to be tested is a non-defective product. Thus, in this type of test circuit, the clock generation circuit 110 independent of the low-speed tester is used.
As in the conventional test circuit, a high-speed test using a low-speed tester can be realized by generating a high-speed clock and performing a BIST test.

In this test circuit, a test for confirming the timing of the Clock signal and the Data signal can be performed. That is, in the circuit of FIG. 1, the output signal of the AND circuit 111 is 1-A, the output signal of the delay circuit 113 is 1-B, and the output signal of the AND circuit 114 is 1-C. The signal 1-B is a signal obtained by delaying the signal 1-A by a certain time, and the signal 1-C is a signal 1-A and a signal 1-A.
The waveform is obtained by taking the logical product with B. FIG. 2 shows operation waveforms when the phase difference between the Clock signal and the Data signal is normal. The signal 1-A is a waveform obtained by performing an AND operation of the Clock signal and the Data signal.
If the phase difference of the signal is the normal 90 °, the signal 1-A
Are all 1/4 of the clock cycle.
It has a pulse width for a period. So, for example,
If the delay time of the delay circuit 113 is １ ／ of the clock cycle, a pulse having a ８ cycle width is output to 1-C. Although the pulse width of the signal 1-C is narrow, the number of high-level pulses is the same as that of the signal 1-A. Therefore, the count numbers of the two counters 112 and 115 in FIG.
16 outputs a high level, and it is detected that the timing is normal.

FIG. 3 shows operation waveforms when the phase difference between the Clock signal and the Data signal is abnormal. For example, the delay time of the delay circuit 113 is １ ／ cycle of the Clock cycle, and the phase difference between the Clock signal and the Data signal is C
If there is more than ／ cycle of the lock cycle, the disappearance of the pulse occurs in the waveform 1-C as shown in FIG.
That is, when the high-level pulse width of the output waveform of the AND circuit 111 is shorter than the delay time of the delay circuit 113, the high-level pulse disappears due to the calculation in the AND circuit 114, and as a result, The pulse counts of the counter 112 and the counter 115 are different.
As a result, a difference occurs in the number of pulses of the signals 1-A and 1-C, and as a result, a low level is output from the coincidence detection circuit 116, and an abnormal timing is detected.

FIG. 4 is a time chart when a timing test is performed by a low-speed tester using the test circuit of FIG. BIST is started by inputting a BISTSTART signal from the low-speed tester, and immediately after that, TIM is started.
By releasing the INGRESET signal, the counters 112 and 115 for timing check start counting the number of pulses. After a certain amount of time,
The BIST ends, and the waveform of the Data signal does not change. At that time, whether or not the logic operation of the BIST was normal is output to the BISTFLAG signal, and the Clock
Whether or not the timing of the signal and the Data signal is normal is output to the TIMINGFLAG signal. The BISTFLAG signal and the TIMINGFLAG signal are taken into the tester by the comparators 117 and 119 of the tester, so that the semiconductor integrated circuit 10 to be tested is
It is determined whether 1 is normal in both the logical operation and the timing operation.

Here, in the test circuit of FIG. 1, even when the AND circuit 111 and the AND circuit 114 can be both handled as OR circuits, the same timing check can be performed. In particular, when the state of the Data signal after the end of the BIST is fixed at a high level, the counter 112,
In order not to advance the counting operation of 15, the gates 111 and 114 are preferably formed by an OR circuit. Conversely, when the state of the Data signal after the end of the BIST is fixed at a low level, it is preferable that the logic circuits 111 and 114 be AND circuits.

Next, a second embodiment of the present invention is shown in FIG. In this embodiment, in addition to the circuit of the first embodiment shown in FIG. 1, a circuit for checking the pulse width of a signal obtained by ANDing the inverted signal of the Clock signal and the Data signal is added. That is, in the figure, parts equivalent to those in FIG. AND circuit 511, 514, delay circuit 513, counter 5
12, 515 and a coincidence detection circuit 528 have the same configuration as in the first embodiment, and an AND circuit 522, 525, a delay circuit 524, counters 523, 526, a coincidence detection circuit 527 are connected to this circuit via an inverter 521. Is provided. Then, the coincidence detection circuit 52
7 through the AND gate 528 of the output of the coincidence detecting circuit 516 and the output of the coincidence detecting circuit 516 to output as a TIMINGFLAG signal.

In this test circuit, as shown in the time chart of FIG. 6, the number of timings for checking the phases of the Clock signal and the Data signal doubles.
Therefore, the outputs of the two coincidence detection circuits 516 and 527 are both at the high level, that is, the coincidence detection circuits 516 and 527
TIMINGF only when a match is detected at 27
The LAG signal becomes high level. Further, all the four AND circuits 511, 514, 522, and 525 can be replaced with OR circuits. It should be noted that in the case of the circuit of the present embodiment, the clock cloning is performed by the inverter 521 for inverting the clock signal.
Since the k signal is slightly delayed from the Data signal,
It may be necessary to insert a delay circuit so as to delay the timing at which the Data signal enters the AND gate 522.

[0019]

As described above, the present invention calculates the logical product or logical sum of a clock signal and a data signal, counts the logical outputs, and calculates the logical output of the logical output and its delay output. By counting and seeing the coincidence of these count values, it is possible to test the timing operation of the semiconductor integrated circuit. This makes it possible to test signal timing during high-speed testing, which was not possible with conventional low-speed testers. realizable.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a first embodiment of a test circuit of the present invention.

FIG. 2 is an operation waveform diagram when timing is normal.

FIG. 3 is an operation waveform diagram when timing is abnormal.

FIG. 4 is a time chart of a timing test.

FIG. 5 is a circuit diagram of a test circuit according to a second embodiment of the present invention.

FIG. 6 is an operation waveform diagram when the timing is normal.

FIG. 7 is a circuit diagram of an example of a conventional test circuit.

FIG. 8 is a conventional BIST time chart.

[Explanation of symbols]

101, 501, 701 Semiconductor integrated circuit device 102, 502, 702 High-speed interface circuit 103, 503, 703 BIST circuit 106, 506, 706 90 ° phase modulation circuit 110, 510, 710 High-speed clock generation circuit 111, 511, 711 Logical product Circuit (first AND circuit) 112, 512, 712 Counter (first counter) 113, 513, 713 Delay circuit 114, 514, 714 AND circuit (second AND circuit) 115, 515, 715 Counter (Second counter) 116, 516, 716 Match detection circuit (first match detection circuit) 522 Logical product circuit (third logical product circuit) 523 Counter (third counter) 524 Delay circuit 525 Logical product circuit ( (Fourth AND circuit) 526 counter (fourth counter) 527 one Detection circuit (second coincidence detection circuit) 528 AND circuit (fifth logical product circuit)

Claims (6)

[Claims] 1. The logic of a clock signal for driving a high-speed semiconductor integrated circuit device to be measured and a data signal output at a different timing from the clock signal when the high-speed semiconductor integrated circuit device is driven. A first logical product circuit for calculating a product, a second logical product of the output signal of the first logical product circuit, and a signal obtained by delaying the output signal of the first logical product circuit by a fixed amount An integrated circuit;
A first counting circuit that counts the output of the AND circuit, a second counting circuit that counts the output of the second AND circuit,
A high-speed semiconductor integrated circuit device, comprising: a coincidence detection circuit that compares respective count values of the first and second count circuits and outputs a timing normal signal when both coincide with each other. Test circuit. 2. The logic of a clock signal for driving a high-speed semiconductor integrated circuit device to be measured and a data signal output at a different timing from the clock signal when the high-speed semiconductor integrated circuit device is driven. A first logical product circuit for calculating a product, a second logical product of the output signal of the first logical product circuit, and a signal obtained by delaying the output signal of the first logical product circuit by a fixed amount An integrated circuit;
A first counting circuit that counts the output of the AND circuit, a second counting circuit that counts the output of the second AND circuit,
A first counting circuit that compares respective count values of the first counting circuit and the second counting circuit and outputs a coincidence signal when both coincide with each other;
, A third AND circuit for performing an AND operation of the data signal and the inverted signal of the clock signal, an output signal of the third AND circuit, and an output of the third AND circuit The fourth operation is to AND the signal with the signal delayed by a certain amount.
AND circuit, a third counting circuit for counting the output of the third AND circuit, a fourth counting circuit for counting the output of the fourth AND circuit, and the third counting circuit And a second coincidence detection circuit that compares each count value of the fourth counter circuit and outputs a coincidence signal when the two coincide with each other.
And a fifth AND circuit that outputs a normal timing signal when a match signal is output from each of the match detection circuit of (1) and (2). 3. The test circuit for a high-speed semiconductor integrated circuit device according to claim 1, wherein said first and second AND circuits are respectively replaced by OR circuits. 4. The test circuit for a high-speed semiconductor integrated circuit device according to claim 2, wherein each of said first to fourth AND circuits is replaced by an OR circuit. 5. The semiconductor integrated circuit device includes a circuit that performs a self-diagnosis based on an input high-speed clock signal, and the self-diagnosis circuit diagnoses that the logic operation of the semiconductor integrated circuit device is normal. 6. The test circuit for a high-speed semiconductor integrated circuit device according to claim 1, wherein a logic normal signal is output at a time. 6. The low-speed tester according to claim 1, further comprising a low-speed tester that executes a test of the semiconductor integrated circuit device by using a logic normal signal output from the self-diagnosis circuit and the timing normal signal as inputs. A test circuit for the high-speed semiconductor integrated circuit device according to claim 1.