JPH0366624B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to integrated circuits with test functionality.

[Technical background of the invention and its problems]

Recently, there has been a trend towards further miniaturization of integrated circuits.
Along with this, ultra-high speeds are being promoted.

Therefore, in conventional integrated circuits, an appropriate input pattern is given, pass/fail is determined based on whether the output pattern matches the correct answer pattern, and if the output pattern does not match the correct answer pattern, the test is considered to be defective. or the output pattern is 0 or 1
A so-called delay time test is performed to test whether the timing determined by the input pattern, that is, the time from the moment an input pattern is applied to the appearance of an output pattern, satisfies a specification value.

However, as the speed of integrated circuits increases, the time from input to output becomes extremely short, so conventional IC testers cannot handle this, and for this reason, new testers for high-speed integrated circuits have to be developed. is desired. However, developing a new high-speed IC tester like this had the disadvantage of increasing the economic burden.

[Purpose of the invention]

This invention was made in view of the above circumstances,
An object of the present invention is to provide an integrated circuit having a test circuit that enables high-speed testing.

[Summary of the invention]

A test circuit is provided which has means for generating a high-speed clock for the internal logic having the circuit under test, means for generating a low-speed clock obtained by dividing the high-speed clock, and selection means for selecting either the high-speed clock or the low-speed clock. In test pre-processing mode, select a low-speed clock using the selection means, prepare an input pattern using this low-speed clock, then select a multi-cycle high-speed clock using the selection means in test execution mode, and select the first high-speed clock. The input pattern is input to the circuit under test at , and the output pattern of the circuit under test is taken in at the subsequent high-speed clock, and this output is then read out at the low-speed clock in the test pre-processing mode for test judgment. ing.

〔Effect of the invention〕

Optimal test results can be obtained even for high-speed integrated circuits, and it is also economically advantageous because only a small-scale circuit dedicated to testing is incorporated. It also has the advantage of being able to perform tests over multiple cycles as a test execution mode.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows a case where the entire internal logic is the circuit under test.

In the figure, 1 is an internal logic, and this internal logic 1 has an input register 2 on the input side and an output register 3 on the output side.

On the other hand, 4 is an oscillation circuit, and this oscillation circuit 4 includes, for example, an odd number of knot circuits connected in series to oscillate a high-speed clock. A frequency dividing circuit 5 for dividing the frequency of the high speed clock is connected to the output terminal of this oscillation circuit 4. In this case, the frequency divider circuit 5 divides the frequency of the high-speed clock to 1/4 to generate a low-speed clock.
It has two flip-flops 51 and 52.

The output terminal of the oscillation circuit 4 is connected to one input terminal of the first selection circuit 6, and the output terminal of the frequency dividing circuit 5 is connected to the other input terminal of the selection circuit 6, and an external output terminal is connected to the output terminal of the oscillation circuit 4. 7 is connected.

The output terminal of the first selection circuit 6 is connected to one input terminal of the second selection circuit 8. This second selection circuit 8 has its other input terminal connected to an external clock terminal 9, its output terminal connected to the internal logic 1, and its selection control terminal connected to a test terminal 10.

Reference numeral 11 denotes a test start terminal for instructing a test execution mode, and this terminal 11 is connected to the D terminal of a test execution flip-flop 13 via an AND circuit 12. This flip-flop 13 becomes "1" in the test execution mode and becomes "0" at the end of the test execution mode.The Q terminal is connected to the selection control terminal of the first selection circuit 6, and the It is connected to the CLR terminals of flip-flops 51 and 52, respectively, and its CLK terminal is connected to the selection control terminal of the second selection circuit 8.

The Q terminal of the flip-flop 13 and the output terminal of the second selection circuit 8 are connected to a counter 15 via an AND circuit 14. This counter 15 is set to a predetermined value in advance, and counts down by one for each cycle of the clock output from the second selection circuit 8 in the test execution mode. It is connected to the AND circuit 12. In this case, the value set in the counter 15 is (number of cycles desired to be executed - 1). Also, the logic required for setting is omitted here.

Next, its effect will be explained.

Now, set the test terminal 10 to "1" to enter the test mode. Then, the second selection circuit 8
The output of the selection circuit 6 is selected. At this time, since the test start terminal 11 is "0", the test execution flip-flop 13 is "0", which is applied to the first selection circuit 6. This causes the first selection circuit 6 to select the output of the frequency divider circuit 5, and this output is outputted via the second selection circuit 8. In this case, the second
When the high-speed clock shown in Figure 2a is output, the frequency divider circuit 5 divides the frequency of this high-speed clock to 1/4 as shown in Figure 2B.
The low-speed clock shown in is generated. Therefore, at this time, the low speed clock shown in FIG. At this time, the counter 15 is set to 1 if the number of cycles desired to be executed in the test execution mode is, for example, 2 cycles.

In this state, if "1" is input to the test start terminal 11 as shown in FIG. 2c and the test execution flip-flop 13 is set to "1" as shown in FIG. 2d, then the first selection circuit 6 is the oscillation circuit 4
The high-speed clock is selected and this clock is output from the second selection circuit 8, thereby entering the test execution mode using the high-speed clock shown in FIG. 2(f). In this case, the input pattern is input to the register 2 at the first high speed clock. Then,
An input pattern is applied to the internal logic 1 through this register 2, and after a predetermined period of time, an output pattern appears on the output side, and this output pattern is taken into the output register 3 at the next high-speed clock.

In this test execution mode, the counter 15 counts down each time a clock is input via the AND circuit 14. When the count reaches 0, a "1" output as shown in FIG.
When the value is set to "0", the test pre- and post-processing mode is set again. Then, a low-speed clock is generated again, and the contents of the output register 3 are read out using this low-speed clock. Therefore, from the contents of this output register 3, a test result of a logic function to determine whether an accurate output pattern has been obtained for an input pattern can be obtained, and the time between two high-speed clocks, that is, a predetermined tolerance can be obtained. A delay time test result is obtained to determine whether the output pattern appears within the delay time.

Thereafter, "1" is set to the test start terminal 11 in the same manner.
The above test execution mode will be obtained each time you input .

Thereafter, when all tests are completed, the test terminal 10 is set to "0", and the second selection circuit 8 directly selects the input from the external clock terminal 9, and henceforth enters the normal mode.

Here, the AC characteristics can be tested by measuring the output of the external output terminal 7, that is, the low-speed clock of the frequency dividing circuit 5. At this time, the AC characteristics can be tested independently of the test mode and normal mode.

Therefore, with this configuration, a high-speed clock can be obtained in the test execution mode as well as a low-speed clock in the test pre-processing mode for the internal logic having the circuit under test, so that such a high-speed clock can be used as a clock for measuring delay time. By using this method, it is possible to accurately determine delay times, and optimal test results can be expected for high-speed integrated circuits. In addition, since the low-speed clock is obtained by dividing the high-speed clock, it can be obtained as an accurate clock corresponding to the high-speed clock. This allows for reliable preparation of input patterns and reading of output patterns in test pre-processing mode. can. Furthermore, since the low-speed clock can be self-sufficient within the test circuit, there is an advantage that an external low-speed clock generation source can be made unnecessary. Furthermore, since high-speed integrated circuits can be tested simply by incorporating a small-scale test-dedicated circuit, it is extremely economically advantageous compared to developing a new high-speed tester. Furthermore, in the test execution mode, a high speed clock with multiple cycles is available, so that tests can be performed over multiple cycles.
Additionally, since the low-speed clock of the frequency divider circuit is output externally, the AC characteristics can be tested from this output. In this case, by using the output of the first selection circuit, the AC characteristics can be tested not only by a low-speed clock but also by a high-speed clock.

It should be noted that the present invention is not limited to the above-mentioned embodiments, but can be implemented with appropriate modifications without changing the gist. For example, in the above description, we have described the case where the high-speed clock is 2 cycles, but if the internal logic includes a flip-flop or the like and the output pattern cannot be immediately determined for the input pattern and requires several clocks, a high-speed clock of several cycles may be applied. .
In this case the high speed clock is also provided to the internal logic. Further, in the above embodiment, the case where the entire internal logic is to be tested has been described, but the present invention can also be applied to a case where a circuit under test included in a part of the internal logic is to be tested.

[Brief explanation of drawings]

FIG. 1 is a schematic configuration diagram showing an embodiment of the present invention, and FIG. 2 is a time chart for explaining the embodiment. 1...Internal logic, 2...Input register, 3
... Output register, 4 ... Oscillator circuit, 5 ... Frequency divider circuit, 6, 8 ... Selection circuit, 7 ... External output terminal, 9 ... Clock terminal, 10 ... Test terminal,
11...Test start terminal, 12, 14...AND circuit, 13...Test execution flip-flop, 1
5...Counter, 16...Not circuit.

Claims (1)

[Scope of Claims] 1. An internal logic having a circuit under test, means for generating a high-speed clock, means for dividing the frequency of the high-speed clock to generate a low-speed clock, and either the high-speed clock or the low-speed clock. and a selection means for selecting a low-speed clock as a test pre-processing mode and a high-speed clock as a test execution mode by the selection means, thereby making it possible to perform various tests on the circuit under test. An integrated circuit featuring: 2. The internal logic has an input register and an output register, and the input pattern prepared at the low-speed clock in the test pre-processing mode is input to the input register at the first high-speed clock in the test execution mode, and continues. Claim 1, characterized in that the output pattern of the internal logic is taken into an output register by a high-speed clock, and the contents of the output register are read out by a low-speed clock in a subsequent test pre-processing mode. integrated circuit. 3. The integrated circuit according to claim 1 or 2, wherein the means for generating the high-speed clock is an odd number of knot circuits connected in series. 4 Claims 1 to 3, characterized in that the output of the selection means can be outputted to the outside.
An integrated circuit according to any of paragraphs.