JP2000304816A - Logic integrated circuit with diagnostic function and its diagnostic method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To test a delay of an internal logic circuit with high precision by forming two clock signals at different timing fed to FF for a scan path system test on the basis of a clock signal to a boundary scan test circuit. SOLUTION: A logic LSI with a diagnostic function is provided with a clock forming circuit 61 forming two clock signals TCK1, TCK2 for a shift scan test in an internal logic circuit on the basis of a clock signal TCK fed from the outside for a boundary test in a boundary scan control circuit 16, for example. The circuit 61 is constructed of a differential circuit detecting trailing and leading edges of the clock signal TCK respectively for detecting a pulse and a one-shot pulse generator, for example. In addition, for instance, the circuit 61 may be constructed so that it can select either of the clock signals CK1, CK2 inputted from external terminals 21, 21.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a diagnostic technique for a semiconductor logic integrated circuit, and more particularly to a technique effective when applied to a scan test in a logic integrated circuit incorporating a boundary scan type test control circuit.

[0002]

2. Description of the Related Art Conventionally, there is a logic integrated circuit provided with a diagnostic function of a shift scan system. The shift scan type diagnostic circuit connects flip-flops constituting the original function of a logic integrated circuit in a serial form to enable a shift register (scan path) to be constructed. Scanning data and putting data directly into the logic circuit to operate, and at the same time scanning out data held in flip-flops to output pins using shift registers, improves efficiency. It is a technology that can make a good diagnosis.

[0003] In recent years, the logic of logic integrated circuits has been increasing in scale, so that the number of test patterns required to achieve a desired failure detection rate has become very large. The input method has become incapable. Therefore, a BIST in which a test pattern generation circuit such as a pseudo random number generation circuit is built in a logic integrated circuit.
(Built-in self-test) diagnostic techniques have been proposed. In addition to the BIST diagnostic circuit, a diagnostic method called a boundary scan test for diagnosing a connection state between boards or another semiconductor integrated circuit chip on the board has been proposed.

[0004]

In a conventional shift scan type diagnostic circuit, a scan flip-flop has a master / slave configuration and operates using two clock signals. It was configured to provide two clock signals to the circuit chip. However, the tester and the logic integrated circuit are connected by a cable or the like having a length of several meters, and a clock signal is supplied through the cable. It became clear that there was a problem that a high-precision delay test of a logic circuit could not be performed.

An object of the present invention is to enable a highly accurate delay test of an internal logic circuit in a logic integrated circuit having a built-in diagnostic circuit.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0007]

The outline of a typical invention among the inventions disclosed in the present application is as follows.

That is, some semiconductor integrated circuits are provided with a boundary scan test circuit for diagnosing a connection state between boards or another semiconductor integrated circuit chip on the board.

The present invention is based on a clock signal input from the outside for a boundary scan test circuit.
It is configured to form two clock signals at different timings supplied to flip-flops for a scan path test.

Specifically, a clock forming circuit is provided for the boundary scan test circuit, which forms independent pulses at the rising edge and the falling edge of the clock signal input from the outside. The timing of the two clock signals to be formed is adjusted by changing the duty ratio of the clock signal input from the outside. The clock forming circuit can be constituted by, for example, a differentiating circuit or a one-shot pulse generating circuit.

According to the above means, two clock signals to be supplied to the flip-flops constituting the scan path are formed based on the clock signal input from the outside, so that the external tester and the logic integrated circuit There is no clock skew in cables connecting between
As a result, a highly accurate delay test of the internal logic circuit can be performed.

The timing of two clock signals for operating the internal scan test flip-flop is as follows:
Since the timing can be changed by changing the pulse width or duty ratio of the clock signal input from the outside, the timing can be easily set and changed. Moreover,
Since the clock signal for the scan test is formed using the clock signal for the boundary scan test circuit, the number of external terminals can be reduced, and small-scale circuits such as a differentiation circuit and a one-shot pulse generation circuit can be used. By simply adding a simple circuit, a clock signal for operating the scan test flip-flop can be formed, and a large increase in chip area can be suppressed.

Further, in addition to a circuit for forming two clock signals supplied to the internal scan test flip-flop based on a clock signal for a boundary scan test circuit input from the outside, an internal scan test flip-flop May be provided with an external terminal for inputting two clock signals for operating the clock signal and a selection circuit for selecting one of the clock signals.
As a result, diagnosis using a conventional scan path type tester can also be performed, and the range of choices for the user is widened.

The clock selection state of the selection circuit can be set by a register provided in a control circuit for an internal scan test. Thereby, it is possible to set as to which clock is to be used for diagnosis as required.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows a configuration of a diagnostic circuit portion of a logic LSI having a diagnostic function according to the present invention. Although not particularly limited, each circuit block shown in the figure is a single semiconductor chip 1 such as single crystal silicon.
0 is formed by a known semiconductor manufacturing technique.
In addition, as an example, an example applied to a logic LSI including a BIST-type diagnostic circuit is shown.

In this embodiment, reference numeral 11 denotes an internal logic circuit configured to have a desired logic function.
1, FF12... FFmn represent flip-flops constituting this internal logic circuit, 12 represents a pattern generator such as a pseudo-random number generator that generates a test pattern at the time of diagnosis, and 13 compresses a test result. And a pattern compressor 14 for outputting these patterns.
2. Pattern compressor 13 and flip-flop FF1
1 is a self-diagnosis control circuit that controls a scan test by controlling FFmn.

The flip-flops FF11 to FFmn
In addition to the normal latch function, a circuit of a type that can configure scan paths ISP1, ISP2,... ISPm as shown in FIG. It takes in data output from a gate circuit or the like and outputs it to the next-stage logic gate circuit. At the time of the scan test, the scan data is controlled so as to form a scan path including a shift register (F / F chain) as shown in FIG.
P2: Shifted along ISPm. The pattern compressor 13 is configured to control the scan paths ISP1, ISP2,.
It has a function of code-compressing bit data sent through ISPm and outputting it as serial data. Since the output serial data has a unique value in the case of normal, the LSI tester can determine normal / abnormal by holding this value in advance and comparing it with the serial data.

As shown in FIG. 1, in the logic LSI of this embodiment, in addition to the above-mentioned self-diagnosis circuit, a connection state between boards or another semiconductor integrated circuit chip on the board is diagnosed. Interface circuit 1 provided with flip-flops and input / output buffers that can constitute a boundary scan shift register (BSP chain)
5 and a boundary scan control circuit 16 are provided. The boundary scan control circuit 16 is configured to execute a process according to the contents when an instruction code is input to the boundary scan control circuit 16 by designating a test mode from the outside.

In FIG. 1, reference numeral 17 denotes an input / output circuit comprising a buffer for inputting / outputting signals for the internal self-diagnosis function and the boundary scan function. Also,
TMS is an input terminal of a control signal for designating a boundary test mode or its signal (hereinafter the same), T
DI is an input terminal for test data for a boundary test, TCK is an input terminal for a clock signal for a boundary test, TDO is an output terminal for test data, and TRST.
Is a reset input terminal to the boundary scan control circuit 16, M3 to M6 are mode control input signal input terminals to the self-diagnosis control circuit 14, clock signal input terminals for scan tests of the CK1 and CK2 internal logic circuits, and AE. Is the self-diagnosis control circuit 1 when performing the acceleration test.
4 is an enable signal to be input.

FIG. 2 shows a schematic configuration of a main part of the present invention and a schematic configuration of the self-diagnosis control circuit 14.

According to the present invention, a boundary scan control circuit 1 is provided.
6, two clock signals TC for a shift scan test of an internal logic circuit based on a clock signal TCK externally supplied for a boundary scan test.
A clock forming circuit 61 for forming K1 and TCK2 is provided. The clock forming circuit 61 can be constituted by, for example, a differentiating circuit or a one-shot pulse generating circuit that detects a falling edge and a rising edge of the clock signal TCK to form a pulse.

Although not particularly limited, in this embodiment, external terminals 21 and 22 for inputting two clock signals CK1 and CK2 for operating the internal scan test flip-flop are also provided. Any one of the clocks is selected in the diagnosis control circuit 14 and the internal scan test flip-flops FF11 to FFm
n and can be operated.

The self-diagnosis control circuit 14 has a test mode setting register 41 which can be set based on an external signal.
And the clock TCK1, TCK2 or CK1, C
And a selector control signal CK for selecting which clock is to be selected according to one bit in the test mode setting register 41.
S is formed. Further, the selector 42 performs the operation of selecting the clock indicated by the selection control signal CKS based on the selection timing control signal RTI from the boundary scan control circuit 16. Then, when the selection timing control signal RTI is set to a low level, the selector 42 operates so as not to transmit any clock. The register 41 includes input terminals M3 to M3 for the mode designating control signal.
6 is set according to the state.

Further, the self-diagnosis control circuit 14 includes a RAGR control circuit 43 for forming a control signal for the pattern generator 12, a MISR control circuit 44 for forming a control signal for the pattern compressor 13, and an internal scan path ISP1. ,
ISP2... ASLD control circuit 45 for forming a control signal for operating ISPm, and BSR for forming a control signal for operating a boundary scan path by self-diagnosis
A control circuit 46 and a decoder 47 for decoding the contents of the test mode setting register 41 and forming a signal for controlling the operation state (mode) of each of the control circuits 43 to 46 are provided.

FIG. 3 shows a boundary scan control circuit 1
6 is shown. The boundary scan control circuit 16 of this embodiment includes a test mode control signal TMS input from outside in addition to the clock formation circuit 61.
, A control register 63 for holding a control code output from the random logic circuit 62, and decoding a control code held in the control register 63 to output a predetermined control signal. Control decoder 64, test data input terminal TD
It comprises an instruction register 65 for taking in data input from I based on a control signal output from the control decoder 64.

The control register 63 and the control decoder 64 operate with, but not limited to, a clock signal TCK supplied from the outside. The instruction register 65 is constituted by a shift register. When the shift register code of the instruction register is held in the control register 63, the held data is stored in the control register 63 based on a control signal output from the control decoder 64.
Output while shifting bit by bit.

The random logic circuit 62 is connected to an external test mode control signal TMS and a control register 63.
The control signal is generated and output based on the feedback signal from the controller. Instead of the random logic circuit, a ROM (read only memory) for storing a micro control code can be used.

The boundary scan test performed by the boundary scan control circuit 16 is performed by flip-flops provided corresponding to input / output terminals connected to another logic LSI on the board on which the logic LSI 10 is mounted. To the boundary scan register
Test data input to a test data input terminal TDI by a tester or the like via an input / output terminal is scanned in from the boundary scan control circuit 16 and output to another logical LSI, or a boundary scan register output from another logical LSI and output. In this case, the input data taken into the device is scanned out, read into the boundary scan control circuit 16, output from the test data output terminal TDO, and determined by a tester or the like.

In order to perform the shift scan test of the internal logic circuit by the logic LSI of this embodiment, first, the test mode control signal TMS is applied to the control register 63 in the boundary scan control circuit 16 and the instruction register 65 to the instruction register 65. A predetermined control code for inputting an instruction code is set, and an instruction code for executing a scan test is input to the instruction register 65.

Next, the control register 63 is caused to hold a control code for validating the instruction code in the instruction register 65. Then, according to the instruction code in the instruction register 65, the self-diagnosis control circuit 14 starts a predetermined control operation, and the flip-flop FF11 in the internal logic circuit 11 starts.
FFmn operate as a shift register, a control signal is generated, and the pattern generator 12 is activated to generate a random test pattern, which is a flip-flop FF11 to FFm constituting a scan path.
n, and the flip-flops FF11 to FFmn perform a scan operation to shift data toward the pattern compressor 13. Then, when the desired data reaches the pattern compressor 13, the scanning operation is stopped, and the boundary scan control circuit 16 sends the test data output terminal TD
The test result is output to O.

The control when the test is performed by operating the boundary scan shift register (BSP chain) in the self-diagnosis mode is almost the same as described above. The shift scan test of the internal logic circuit can be started by externally applying a signal to the mode designation control terminals M3 to M6.

FIG. 4 shows, as an example of the clock forming circuit 61, a one-shot pulse generating circuit O for detecting a falling edge of the clock signal TCK and forming a pulse.
FIG. 5 shows a schematic configuration in the case of comprising a one-shot pulse generation circuit OPG2 for forming a pulse by detecting a rising edge, and FIG. 5 shows a specific example of the one-shot pulse generation circuit. Among them, FIG.
Is a one-shot pulse generation circuit OPG1, which detects a rising edge of the clock signal TCK and forms a pulse.
(B) shows a one-shot pulse generation circuit OP for detecting a falling edge of the clock signal TCK and forming a pulse.
G2.

As shown in FIG. 5, each of the one-shot pulse generating circuits OPG1 and OPG2 receives an input inverter 611, a delay inverter array 612, and two signals respectively passed through these circuits. NAND gate circuit 613 as a signal and output inverter 614
It is composed of The difference between the one-shot pulse generation circuits of FIGS. 5A and 5B is that the circuit of FIG. 5A has two stages of input inverters 611, whereas the circuit of FIG. The only difference is that it is composed of one stage. The width of the pulse generated by the delay time of the delay inverter train 612 is determined.

FIG. 6 shows internal scan paths ISP1, ISP
SP2... A specific example of a circuit configuration of the ASLD control circuit 45 for forming a control signal for operating the ISPm is shown.

The ASLD control circuit 45 includes a NAND gate 451 using the signals / SS CMN and / CA CMN as input signals, and a NAND gate 45 using the signals CA CMN and SELCK1 as input signals.
2, the NAND gate 453 having the signals SS CMN and SELCK1 as input signals, the signal SELCK2 and the NAND gate 451.
A NAND gate 454 having the output signal of
An inverting input type OR gate 455 using the signal / Nrm CMN and the output signal of the NAND gate 452 as input signals, an inverting input type OR gate 456 using the signal / Nrm CMN and the output signal of the NAND gate 454 as input signals, It comprises output inverters 457 to 459.

Here, the input signal / Nrm CMN, SS CMN, CA
CMN is a signal supplied from a decoder 47 for decoding the value of the mode setting register 41 shown in FIG.
One of these signals is set to a high level. When the signal / Nrm CMN is at a high level, it indicates the normal mode, that is, the non-test mode, and the signal CA
When CMN is at a high level, it indicates a mode for taking in data in the internal logic circuit. When the signal SS CMN is at a high level, the internal scan paths ISP1, ISP2,.
This indicates a mode in which the SPm performs a scan operation. SELCK1 and SELCK2 are clock signals selected and supplied by the selector 42 shown in FIG.

FIG. 7 shows internal scan paths ISP1, ISP
SP2... Flip-flop FF1 constituting ISPm
Specific examples of 1 to FFmn are shown. As shown in the figure, each flip-flop has a double latch configuration of a master latch FF1 and a slave latch FF2.

The master latch FF1 has two data input terminals D and SID and two clock terminals CK and CK for giving data latch timing to the data input terminal D.
MC1; a clock terminal SWI for giving data latch timing to the data input terminal SID; and one output terminal qm. The data input terminal D receives a signal from a preceding logic gate constituting an internal logic circuit, and the data input terminal SID receives a signal from a preceding flip-flop constituting a scan path. Further, a clock signal TCK for a boundary scan control circuit is input to the clock terminal CK. further,
Signals output from the inverters 457 and 458 of the ASLD control circuit 45 are input to the clock terminals MC1 and SWI.

On the other hand, the slave latch FF2 has a data input terminal dm connected to the data output terminal qm of the master latch FF1, a clock terminal C2 for giving data latch timing to the data input terminal dm, and two output terminals Q , SOD. The output terminal Q is
The output terminal SOD is connected to the data input terminal of the subsequent flip-flop forming the scan path, and the output terminal SOD is connected to the input terminal of the subsequent logic gate forming the internal logic circuit.
Further, a signal output from the inverter 459 of the ASLD control circuit 45 is input to the clock terminal C2.

FIG. 8 shows internal scan paths ISP1, ISP
SP2... Flip-flop FF1 constituting ISPm
1 to FFmn to scan input test data and output the output of the logic gate in the internal logic circuit to the flip-flop FF
The timing of each clock signal when the data is fetched into 11 to FFmn and the fetched data is scanned and output is shown (the signal / Nrm CMN is low level in the test mode).

When test data is scanned and input, with the signal SS CMN at a high level and the signal CA CMN at a low level, the data held in the master latch FF1 is first taken into the slave latch FF2 by the clock C2, The data of the scan-in data input terminal SID is taken into the master latch FF1 by SWI. By repeating this, the test data is sequentially shifted by the flip-flops on the scan path.

When the scan input of the test data is completed, the signal SS CMN goes low and the signal CACMN goes high, and the data held in the master latch FF1 is taken into the slave latch FF2 at clock C2. Is taken into the master latch FF1 from the data input terminal D.

Next, when the signal SS CMN is at the high level and the signal CA C
With MN at a low level, the clocks C2 and S
By giving WI to the flip-flops FF11 to FFmn alternately, the data captured by the flip-flops FF11 to FFmn is shifted along the scan path. Thus, the operation result of the internal logic circuit based on the scan-in data can be output via the scan path.

According to the timing shown in FIG.
Input data is given to the logic gate in the internal logic circuit at the rising timing of the clock TCK, and the output of the logic gate in the internal logic circuit can be taken into the flip-flop constituting the scan path after T time. By setting the width to the actual level (design delay time) of the signal path at the diagnostic location by a tester and performing a test, it is diagnosed whether each signal path of the internal logic circuit operates with the designed delay time (delay). be able to. Further, by repeating the test while changing the pulse width of the clock TCK, the maximum operation speed of the target logic LSI can be known.

As described above, in the above embodiment, based on the clock signal externally input to the boundary scan control circuit, two different timings supplied to the flip-flops constituting the scan path of the internal logic circuit are set. Since it is configured to form one clock signal, there is no clock skew in a cable or the like connecting between an external tester and a logic integrated circuit, thereby enabling a highly accurate delay test of an internal logic circuit to be performed. .

The timing of the two clock signals to be formed is adjusted by changing the duty ratio of the clock signal input from the outside, so that the timing can be easily set and changed. become. In addition, since the clock signal for the scan test is formed by using the clock signal input to the boundary scan control circuit, the number of external terminals can be reduced, and the difference between the differential circuit and the one-shot pulse generation circuit is eliminated. The clock signal for operating the scan test flip-flop can be formed only by adding a small-scale circuit, and there is an effect that a significant increase in the chip area can be suppressed.

Further, in addition to a circuit for forming two clock signals supplied to the internal scan test flip-flop based on a clock signal input from the outside, two clock signals for operating the internal scan test flip-flop Is provided, and a selection circuit for selecting any one of the clock signals is provided, so that diagnosis using a conventional scan path type tester can also be performed, and the range of selection for the user is provided. Becomes wider.

Although the invention made by the inventor has been specifically described based on the embodiments, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the gist of the invention. Needless to say. For example, in the above embodiment, the flip-flop F constituting the internal logic circuit
The case has been described where F11 to FFmn are connected so as to form an m-column scan path. However, the present invention can also be applied to a case where F11 to FFmn are connected so as to form one scan path.

In the above description, the invention made mainly by the present inventor is described by using the logic L
Although the description has been given of the case where the present invention is applied to the SI, the present invention is not limited to this. The present invention can be applied to an LSI in which a digital circuit and an analog circuit are mixed and other semiconductor integrated circuits in general.

[0051]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, according to the present invention, in a logic integrated circuit having a built-in diagnostic circuit, there is an effect that a highly accurate delay test of an internal logic circuit can be performed.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a schematic configuration of a diagnostic circuit portion of a logic LSI having a diagnostic function according to the present invention.

FIG. 2 is a block diagram showing a schematic configuration of a self-diagnosis control circuit in a logic LSI to which the present invention is applied, and a relationship between the self-diagnosis control circuit and a boundary scan control circuit.

FIG. 3 is a block diagram illustrating a schematic configuration of a boundary scan control circuit.

FIG. 4 is a block diagram showing a schematic configuration when a one-shot pulse generation circuit is used as an example of a clock forming circuit;

FIG. 5 is a logic configuration diagram showing a specific example of a one-shot pulse generation circuit constituting the clock forming circuit.

FIG. 6 is a logical configuration diagram showing a specific circuit configuration example of an ASLD control circuit that forms a control signal for operating an internal scan path.

FIG. 7 is a diagram showing a schematic configuration of a flip-flop forming an internal scan path.

FIG. 8 is a timing chart showing the timing of each clock signal when performing a delay test in an internal logic circuit using an internal scan path.

[Description of Signs] ISP1 to ISPm scan path FF11 to FFmn flip-flop capable of configuring scan path 10 logic LSI 11 internal logic circuit 12 pattern generator 13 pattern compressor 13 BIST control circuit 14 self-diagnosis control circuit 16 boundary scan control circuit 17 I / O circuit 41 Mode setting register 42 Selector 45 ASLD control circuit 61 Clock formation circuit 62 Random logic circuit 63 Control register 64 Control decoder 65 Instruction register

Continued on front page F-term (reference) 2G032 AA01 AA04 AC10 AD06 AD07 AG04 AG07 AK16 AK19 5B048 AA20 CC11 CC18 DD05 DD07 EE08 FF01 5J056 AA39 BB60 CC00 CC05 CC18 FF01 FF07 9A001 BB05 HZ34 JJ45 LL05

Claims (5)

[Claims] A first diagnostic circuit for diagnosing the internal logic circuit using a scan path provided in the internal logic circuit, and an external device using a scan path provided in an external interface unit. A second diagnostic circuit for diagnosing connection, comprising: a second diagnostic circuit for diagnosing connection based on a clock signal input from outside for the first diagnostic circuit; A logic integrated circuit with a diagnostic function, comprising: a clock forming circuit for forming a plurality of clock signals for use. 2. The clock forming circuit according to claim 1, wherein the clock forming circuit is a pulse forming circuit that forms independent pulses at rising edges and falling edges of the externally input clock signal. Logic integrated circuit with diagnostic function. 3. An external terminal for receiving a plurality of clock signals for the operation of the second diagnostic circuit, and a clock signal input from the external terminal or a clock signal formed by the clock forming circuit. 3. The logic integrated circuit with a diagnosis function according to claim 1, further comprising a selection circuit for selecting and supplying the selected diagnosis circuit to the second diagnosis circuit. 4. The first diagnostic circuit includes: a pattern generating circuit that generates a test pattern to be supplied to a scan path in the internal circuit; and a control circuit that controls the pattern generating circuit. 4. The logic integrated circuit with a diagnosis function according to claim 3, further comprising a register which can set which clock is selected by the selection circuit based on an external signal. 5. A first diagnostic circuit for diagnosing the internal logic circuit by using a scan path provided in the internal logic circuit, and communicating with an external device by using a scan path provided in an external interface unit. A second diagnostic circuit for diagnosing the connection, and two clock signals having different timings for operating the second diagnostic circuit based on a clock signal input from the outside for the first diagnostic circuit. A clock forming circuit to form a logic integrated circuit, wherein the timing of two clock signals formed for the operation of the second diagnostic circuit is adjusted by adjusting the timing of a clock signal input from the outside. A method for diagnosing a logic integrated circuit, wherein the method is performed by changing a pulse width.