JPH1123660A - Test simplifying circuit of integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To perform the timing verification of a combinational circuit without creating test patterns to it in an integrated circuit designed by scanning. SOLUTION: The test signal value of a combinational circuit 102 is set to each scan flip flop 103 via a scan line 110. Next, by selecting switches 107, the output of the inverted output terminal NQ of each flip flop 103 is inputted two times to its own terminal DT of the flip flop 103 to set the propagation starting timing of a test signal value. After a predetermined time from the propagation starting timing, by a selecting signal of a terminal 104, the output of the combinational circuit 102 is captured in the D terminal of each scan flip flop 103 and outputted to the outside via the scan line 110. The above operation is repeated at the differentiated predetermined times. By comparing each value outputted to the outside with a desired value, it is possible to grasp the total value of delay of the combinational circuit 102.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integrated circuit test facilitating circuit for easily performing AC timing verification and analog characteristic evaluation of an integrated circuit designed by scan design or boundary scan design.

[0002]

2. Description of the Related Art In general, a scan-designed integrated circuit has a configuration in which flip-flops of a sequential circuit can be scanned, and each flip-flop is connected by a scan line, and these are connected to an external input terminal and an external output terminal. By setting the value of each scan flip-flop to an arbitrary value or by outputting the value of each scan flip-flop to the outside, it is possible to easily perform the inspection.

[0003] By performing such a design for facilitating inspection, it is easy to create a pattern for verifying the function of an integrated circuit.
esign Automation) tool (ATPG (Automatic TestP
Attern Generator) can automatically generate a test pattern with a high detection rate.

[0004]

However, in recent years,
Logic circuits are becoming more complicated as semiconductor integrated circuits become more sophisticated and faster. Therefore, even if the function is sufficiently verified by realizing testability by using scan design or the like, the integrated circuit may not operate correctly at a desired operation speed due to the timing of signal transmission and reception. One of the causes
First, the logic of a combinational circuit located between two flip-flops or between an input / output terminal and a flip-flop is complicated, and the delay time of a gate and a wiring is long. Therefore, it is important to verify the timing of the combinational circuit to confirm that the integrated circuit operates correctly at a desired operation speed.

However, in an integrated circuit designed to be scanned as described above, it is relatively easy to create a test pattern for function verification, but it is difficult to create a test pattern for timing verification. As a result, conventionally,
There has been a problem that it is necessary to create a test pattern for a sequential circuit and perform timing verification without using a scan function.

When a semiconductor integrated circuit includes an analog block such as a DA converter or an AD converter, it may be necessary to evaluate the characteristics of the analog block alone.

However, in order to evaluate the characteristics of a DA converter or the like, it is necessary to change a plurality of signal values at the same time. However, in a scan-designed integrated circuit, a plurality of signal values cannot be changed and set at the same time. There is a problem that it is difficult to evaluate analog characteristics.

SUMMARY OF THE INVENTION The present invention focuses on the above-mentioned problem, and an object of the present invention is to incorporate a test circuit for timing verification into a scan-designed integrated circuit, and use this test circuit to execute two scan flip-flops at an arbitrary speed. By performing timing verification on a combinational circuit or an analog block such as a D / A converter located between input / output terminals and a flip-flop, a semiconductor integrated circuit can be prepared without creating a test pattern for a sequential circuit. Of the present invention is to easily realize the timing verification.

[0009]

In order to achieve the above-mentioned object, the present invention employs a configuration in which a start timing for transmitting a desired test value to a combinational circuit can be set.

That is, an integrated circuit test facilitating circuit according to the first aspect of the present invention is a test facilitating circuit for an integrated circuit which is scan-designed and has a scan flip-flop therein, wherein the state value of the scan flip-flop is changed. , Based on a control signal input from the outside.

According to a second aspect of the present invention, in the circuit for facilitating test of an integrated circuit according to the first aspect, the inverting circuit receives an output signal of an inverting output terminal of a scan flip-flop and a scan signal. A switch is selected from the two signals by a switching signal as a control signal input from the outside and input to the scan flip-flop.

Further, according to a third aspect of the present invention, in the circuit for facilitating test of an integrated circuit according to the second aspect, a combination circuit between two scan flip-flops or between a scan flip-flop and an input / output terminal. Alternatively, an analog block is disposed, and the inverting circuit selects a scan signal according to the switching signal, sets a test signal value in the scan flip-flop, and outputs the output of the inverting output terminal of the scan flip-flop according to the switching signal. Selecting a signal to invert the state value of the scan flip-flop, and further selecting an output signal of an inverted output terminal of the scan flip-flop to invert the state value of the scan flip-flop, Start propagating values to the combinational circuit or analog block And setting the timing.

According to a fourth aspect of the present invention, in the circuit for facilitating test of an integrated circuit according to the third aspect of the present invention, the scan flip-flop is configured such that a predetermined time has elapsed since the start of the propagation of the test value by the inverting circuit. Thereafter, an output value from the combinational circuit or the analog block is captured.

According to a fifth aspect of the present invention, in the circuit for facilitating test of an integrated circuit according to the fourth aspect,
The predetermined time from the test value propagation start timing is:
It is characterized in that a plurality of different times are prepared for each minute time.

According to a sixth aspect of the present invention, in the circuit for facilitating test of an integrated circuit according to the fifth aspect, an output value from a combinational circuit or an analog block incorporated in a scan flip-flop is supplied via a scan line. It is characterized by being output to the outside.

The circuit for facilitating the test of an integrated circuit according to the present invention is a circuit for facilitating the test of an integrated circuit which is designed with a boundary scan and has an update flip-flop arranged around the outer periphery of the core circuit. And
An inversion circuit for inverting the state value of the update flip-flop based on an externally input control signal is provided.

According to an eighth aspect of the present invention, in the circuit for facilitating test of an integrated circuit according to the seventh aspect, the core circuit is scan-designed and has a scan flip-flop therein. The integrated circuit according to any one of claims 2, 3, 4, and 5 is configured as a test facilitating circuit.

According to a ninth aspect of the present invention, in the circuit for facilitating test of an integrated circuit according to the seventh or eighth aspect, the inverting circuit includes an output signal of an inverting output terminal of an update flip-flop. And a scan signal, and one of the two signals is selected by a switching signal as a control signal input from the outside and selected and input to the update flip-flop. I do.

According to a tenth aspect of the present invention, in the circuit for facilitating the test of an integrated circuit according to the seventh or eighth aspect, the boundary lease cancel is provided around the outer periphery of the combinational circuit or the core circuit having the analog block. The boundary scan cell is arranged, the boundary scan cell includes a shift flip-flop and the update flip-flop, and the inverting circuit selects a scan signal that has passed through the shift flip-flop according to the switching signal. After setting the test signal value in the update flip-flop, the switching signal selects an output signal of an inversion output terminal of the update flip-flop to invert the state value of the update flip-flop, and further, Inversion of the update flip-flop And selects the output signal of the terminal by inverting the state value of the flip-flop for the update, and sets the start timing for propagating the test signal value to the combinational circuit or analog blocks.

Further, according to an eleventh aspect of the present invention, in the circuit for facilitating test of an integrated circuit according to the tenth aspect, the shift flip-flop is configured such that a predetermined time elapses from a timing at which the inversion circuit starts transmitting a test value. Thereafter, an output value from the combinational circuit or the analog block is captured.

According to a twelfth aspect of the present invention, in the circuit for facilitating test of an integrated circuit according to the eleventh aspect,
The predetermined time from the test value propagation start timing is:
It is characterized in that a plurality of different times are prepared for each minute time.

With the above configuration, according to the present invention, after a test value of a combinational circuit or the like is given to a plurality of flip-flops, an inversion circuit inverts the state value of each flip-flop (inversion test value). Is given to its flip-flop. Further, the inverted value (test value) of the state value of each flip-flop is again obtained by the inverting circuit.
Is given to its own flip-flop, whereby the start timing for transmitting each test value from each flip-flop to the subsequent combinational circuit or analog block is set at the same time.

Thereafter, when a predetermined time elapses from the propagation start timing, the output value from each of the combinational circuits and the like is fetched into each flip-flop, and this operation is repeated with the predetermined time being different. By comparing and checking each output value with the desired value, the total delay time of the combinational circuit from the gate input of the next-stage combinational circuit to the signal input to the next-stage flip-flop can be grasped. Therefore, timing verification of a combinational circuit or an analog block between scan flip-flops or boundary lease cancellation can be performed without creating a test pattern for timing verification.

[0024]

BEST MODE FOR CARRYING OUT THE INVENTION

(First Embodiment) Hereinafter, a first embodiment of the present invention will be described with reference to FIG.

In FIG. 1, reference numeral 101 denotes an integrated circuit device having a combinational circuit 102 and three scan flip-flops 103. Each scan flip-flop 103 includes a normal input terminal D connected to the output of the combinational circuit 102, a scan terminal DT, a terminal NT for receiving a switching signal (mode switching signal) 104 between the normal input and the scan signal, and an output terminal. It has a terminal Q, an inverted output terminal NQ, and a clock terminal CLK for receiving the clock signal 106. Each flip-flop 103
Is connected to the scan terminal DT via the scan line 110 to the output terminal Q of the preceding flip-flop 103. Scan terminal D of the flip-flop 103 in the first stage
The scan input terminal 105 is connected to T, and the scan output terminal 109 is connected to the output terminal Q of the last-stage flip-flop 103. These components are the same as those of the conventional integrated circuit device shown in FIG.

The integrated circuit device 101 of the present embodiment
Further includes a switch (inverting circuit) 107 corresponding to each scan flip-flop 103. Each switch 1
07 is a switching signal (control signal) that receives the output of the scan input terminal 105 and the output of the inverting output terminal NQ of the corresponding scan flip-flop 103 and is externally input.
According to 108, one of the output signals is selected, and the selected signal is input to the scan terminal DT of the corresponding scan flip-flop 103.

Next, the operation of the present integrated circuit device will be described.

First, each scan flip-flop 103 is set to a shift mode in which a signal is input from a scan terminal DT by a mode switching signal 104, and each switch 107 is set by a switching signal 108.
Is switched to select the scan input terminal 105 side. As a result, the test signal value of the combination circuit 102 between the scan flip-flops is set from the scan input terminal 105 to each scan flip-flop 103 via the scan line 110.

Next, by switching the mode switching signal 108, each switch 107 is switched to select the output of the inverting output terminal NQ of the corresponding scan flip-flop 103, and the switch 107 is switched to the scan terminal DT of each scan flip-flop 103. The output mode of the inverted output terminal NQ (the inverted value of the test signal) is set, and the signal 106 is operated for one clock to toggle the internal state value of each scan flip-flop 103.

Subsequently, the signal 106 is further operated by one clock, and the internal state value of each scan flip-flop 103 is toggled again. Thus, the start timing for transmitting the desired test signal to the combination circuit 102 in the next stage is set. At this time, a signal directly transmitted from the external input to the combinational circuit 102 is also synchronized to determine a desired signal value.

Next, the mode switching signal 104
The scan flip-flop 103 is set to a capture mode in which a normal signal is received from the terminal D. Thereafter, the elapsed time from the clock at which the test value propagation start timing is set is appropriately set, and the signal 106
Is operated for one clock, and each output value from the combinational circuit 102 is taken into each scan flip-flop 103.

Thereafter, the scan flip-flop 103 is set to a shift mode in which a signal is input from the scan terminal DT by a mode switching signal 104, and each switch 10 is set by a mode switching signal 108.
7 is switched to select the scan signal, and the value of each scan flip-flop 103 is changed to the scan line 11.
The output is sequentially taken out from the scan output terminal 109 through 0.

The timing of the clock in the capture mode (ie, the time elapsed from the start of the propagation of the test value) is changed to a slightly different value, and the above operation is repeated, and the value captured in each operation is set to the desired value. Compare with,
If checked, the total delay value of the combinational circuit 102 can be accurately measured. This is the same when the number of the scan flip-flops 103 is three or more.

FIG. 2 shows the timing of the above operation of the integrated circuit device of FIG.

(Modification) FIG. 3 shows a configuration of an integrated circuit device including a scan flip-flop 304 which does not want to toggle the internal state value. In the figure, when the scan flip-flop 103 that wants to toggle the internal state value captures the output of the inverted output terminal NQ, the scan flip-flop 304 that does not want to toggle the internal state value captures the output of the output terminal Q. And does not change the internal state value. That is, the switch 107 ′
In this configuration, the output of the output terminal Q of the scan flip-flop 304 that does not want to toggle the internal state value is input. Other configurations are the same as those in FIG. 1, and thus the same portions are denoted by the same reference numerals and description thereof will be omitted.

FIG. 4 shows the operation timing of the integrated circuit device of FIG. 3 shown in this modification.

FIG. 5 shows an example of the operation timing when the combination circuit 102 is provided between the two scan flip-flops 103. In FIG.
4 is a scan flip-flop 103 and a switch 10
7 shows a circuit obtained by combining the circuit of FIG.

FIG. 6 shows an example of the operation timing when the analog block 604 is provided between the scan flip-flop 103 and the external terminal. In FIG. 6B, reference numeral 605 denotes a measuring instrument connected to an external terminal.
The output of the analog block 604 is measured.

(Second Embodiment) Next, a second embodiment of the present invention will be described.
An embodiment will be described.

FIG. 11 shows the configuration of an integrated circuit device according to the present embodiment, which is an integrated circuit designed by boundary scan.

In the figure, reference numeral 1101 denotes an integrated circuit device designed by boundary scan, and is a core circuit 1.
102, and a plurality (eight in the figure) of boundary lease cells 110 arranged around the core circuit 1102.
3, an input / output buffer 1104 connected to these scan cells 1103, and a TAP controller 1105 having a plurality of boundary scan test terminals 1106. The boundary lease scans 1103 are connected in series by boundary scan lines 1120.

Each boundary lease cancel 1103
Have the same configuration, and the internal configuration is shown in FIG. In the boundary lease cancel 701 shown in FIG. 7, reference numeral 702 denotes a shift flip-flop, 703 denotes an update flip-flop, and 707 denotes a switch. The normal signal of the normal signal input terminal 705 and the scan signal input terminal
The scan signal 06 is switched and selected according to the switch signal 708, and the selected signal is input to the terminal D of the shift flip-flop 702. The output terminal Q of the shift flip-flop 702 is connected to the scan signal output terminal 713 and the terminal D of the update flip-flop 703. Reference numeral 709 denotes another switch that switches and selects a normal signal of a normal signal input terminal 705 and an output of an output terminal Q of the update flip-flop 703 in accordance with a switching signal 710. The resulting signal is output from the output terminal 714 of the boundary lease cancel 701. Incidentally, 70
4 is an input terminal for inputting a reset signal to the reset terminal R of the update flip-flop 703;
Reference numeral 12 denotes the two flip-flops 702 and 703, respectively.
Is a clock signal input terminal to the clock terminal CK. The above configuration is the same as the configuration of the conventional boundary lease cancel shown in FIG.

The boundary lease cancel 701 of this embodiment further includes a third switch (inverting circuit) 715.
Having. The switch 715 receives the output of the output terminal Q of the shift flip-flop 702 and the output of the inverted output terminal NQ of the update flip-flop 703, and receives a switching signal (control signal) 71 input from the outside.
6, one of the two output signals is selected,
The selected signal is updated to the flip-flop 7 for updating.
03 terminal D is output.

Next, the operation of the boundary lease cancel 701 shown in FIG. 7 will be described.

First, the switch 707 is switched by the mode switching signal 708 so as to select the scan signal from the scan signal input terminal 706, and the shift flip-flop 702 is set to the mode for inputting the scan signal. A desired test signal value is set from the scan signal input terminal 706 to the shift flip-flop 702.

Next, the switch 715 is switched by the switching signal 716 so as to select the output of the output terminal Q of the shift flip-flop 702, and the output of the output terminal Q is taken into the update flip-flop 703.

Subsequently, the switch 715 is switched by the switching signal 716 to the update flip-flop 7.
03 so as to select the output of the inverted output terminal NQ, and the update flip-flop 703 switches to the mode of inputting the output of the inverted output terminal NQ (the inverted value of the desired test value). 712 to 1
By operating the clock, the internal state value of the update flip-flop 703 is toggled.

Thereafter, the signal 712 is again operated by one clock, and the update flip-flop 70 is operated.
The internal state value of 3 is toggled. As a result, the start timing for transmitting a desired test signal value to the next combinational circuit is set.

Next, according to the mode switching signal 708,
The switch 707 is switched so as to select the normal signal from the normal input terminal 705, and the normal operation mode is set in which the normal signal is input to the terminal D of the shift flip-flop 702. Then, the elapsed time from the clock of the update flip-flop 703 to which the propagation start timing of the desired test value is set is appropriately set, the signal 711 is operated by one clock, and the core circuit 11 is operated.
An output value from a combinational circuit (not shown) in 02 is taken into a shift flip-flop 702.

Further, according to the mode switching signal 708,
The switch 707 is switched so as to select the scan signal from the scan signal input terminal 706, the scan signal is set to the scan mode in which the scan signal is input to the terminal D of the shift flip-flop 702, and the scan line is activated. An output value from the output terminal Q of the shift flip-flop 702 is extracted from the scan signal output terminal 713 to the outside.

The timing of the clock in the normal operation mode (that is, the elapsed time from the start timing of the propagation of the desired test value) is changed to a slightly different value, and the above operation is repeated. 702
By comparing and checking the input value with the desired value, the total delay value of the combinational circuit can be accurately measured.

FIG. 8 shows the timing of the above operation of the boundary lease cancel 701 in FIG.

(Third Embodiment) Next, a third embodiment of the present invention will be described.
An embodiment will be described.

The integrated circuit device of the present embodiment is a combination of the scan-designed integrated circuit device of the first embodiment and the boundary-scan designed integrated circuit device of the second embodiment. Integrated circuit device. Specifically, in the integrated circuit device 1101 designed for the boundary scan shown in FIG.
The core circuit 1102 employs the scan-designed integrated circuit device shown in FIG. Therefore, the same reference numerals are given to the same portions, and the description of the configuration is omitted.

Hereinafter, the operation of the integrated circuit device according to the present embodiment will be described.

First, the scan flip-flops 103 and 304 are set to a shift mode for inputting a signal from the scan terminal DT by the mode switching signal 104, and the switches 107 and 107 'are switched to the scan signal by the mode switching signal 108. Is set so that a scan signal is input to the terminals DT of the scan flip-flops 103 and 304, and under this shift mode, the scan signal input terminal 1
From 05, the test signal value of the combinational circuit between the flip-flops is set to each of the scan flip-flops 103 and 304 via the scan line 110. at the same time,
In parallel, the TAP controller 1105 also sets a test signal value at the time of the capture operation from the boundary scan test terminal 1106 to the boundary lease scan 1103 having the internal configuration of FIG. 7 through the boundary scan line 1120.

Next, the switching signals 108 and 716 (FIG. 7)
Using the scan flip-flop 103 and the boundary scan cell 110 of the core circuit 1102.
3 are operated by one clock each to toggle each internal state value.

Further, the internal state values of the scan flip-flop 103 and the boundary scan cell 1103 of the core circuit 1102 are toggled by operating again for one clock. As a result, the start timing for transmitting a desired test signal value to the next combinational circuit is set.

Next, the mode switching signal 104 and TA
Under the control of the P controller 1105, the core circuit 110
The scan flip-flops 103 and 304 and the boundary scan cell 1103 are set to the normal operation mode, and under this normal operation mode, an appropriate elapsed time is set from the clock where the test value propagation start timing is set. And operates the combinational circuit 102 for one clock.
Output values from the scan flip-flops 103 and 304 of the core circuit 1102 and the boundary lease scan 1
Import to 103.

Further, the mode switching signal 104
The scan flip-flops 103 and 304 are set to a shift mode in which a signal is input from a scan terminal DT, and each switch 107,
107 ′ is switched to select a scan signal,
The value of each of the scan flip-flops 103 and 304 is transferred to the boundary lease scan 11 via the scan line 110.
03, and in the boundary lease cancel 1103, the switch 709 is switched by the switching signal 710 to select the signal of the normal signal input terminal 705, and each of the scan flip-flops 10
The values of 3 and 304 are sequentially extracted from the scan output terminal 109 to the outside. In parallel with this, the switch 707 is switched to select the scan signal from the scan signal input terminal 706 by the mode switching signal 708 in FIG. Under the shift mode, the output value of the shift flip-flop 702 is controlled by the TAP controller 906 to the scan output terminal 7.
13 to the outside via the boundary scan test terminal 1106.

In the above operation, the timing of the clock for taking in the output value from the combinational circuit 102 (elapsed time from the start of the propagation of the test value) is gradually changed, and the output value for each operation is compared with the desired value. , The total delay value of the combinational circuit 102 can be accurately measured.

In the first embodiment, it is necessary to fix the signal directly propagating from the external input to the combinational circuit 102 to a desired signal value in synchronization with the propagation start timing of the test value. In the present embodiment, it is possible to check the total delay time of the combinational circuit without requiring such special external control.

[0063]

As described above, according to the integrated circuit test facilitating circuit of the present invention, a test pattern is created by verifying the timing of a combinational circuit or an analog block between scan flip-flops or boundary scan cells. This has the effect of being able to be easily implemented without any need.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a test facilitation circuit for an integrated circuit according to a first embodiment of the present invention.

FIG. 2 is a diagram showing operation timings of the test facilitating circuit of the integrated circuit.

FIG. 3 is a diagram showing a configuration of a test facilitation circuit for an integrated circuit which is a modification of the first embodiment.

FIG. 4 is a diagram showing operation timings of the test facilitating circuit of the integrated circuit of the modification.

FIG. 5 is a diagram illustrating an operation example in a case where a combinational circuit is located between two flip-flops in the circuit for facilitating test of an integrated circuit according to the first embodiment;

FIG. 6 is a diagram showing an operation example when an analog block is located between an input / output terminal and a flip-flop in the circuit for facilitating test of an integrated circuit according to the embodiment;

FIG. 7 is a diagram illustrating a configuration of a boundary lease scan provided in a circuit for facilitating test of an integrated circuit according to a second embodiment of the present invention;

FIG. 8 is a diagram showing an operation timing of the boundary lease cancellation.

FIG. 9 is a diagram showing a configuration of a test facilitation circuit for an integrated circuit according to a third embodiment of the present invention.

FIG. 10 is a diagram showing a configuration of a conventional scan-designed integrated circuit.

FIG. 11 is a diagram showing a configuration of an integrated circuit designed by boundary scan according to a second embodiment of the present invention.

FIG. 12 is a diagram showing a configuration of a conventional boundary scan cell.

[Explanation of symbols]

102 Combination circuit 103, 304 Scan flip-flop 107 Switch (inverting circuit) 108 Switching signal (Control signal input from outside) 110 Scan line 604 DA converter 605 Measurement device 701, 1103 Boundary lease cancel 702 Shift flip-flop 703 Update Flip-flop 715 switch (inverting circuit) 716 switching signal (control signal input from outside) 1102 core circuit 1105 TAP controller

Claims (12)

[Claims] An integrated circuit that is scan-designed and has a scan flip-flop therein for testing, wherein the inversion circuit inverts a state value of the scan flip-flop based on an externally input control signal. A test facilitating circuit for an integrated circuit, comprising: 2. The inverting circuit receives an output signal of an inverting output terminal of a scan flip-flop and a scan signal, and switches one of the two signals as a control signal input from the outside. 2. A switch which is selected by a signal and input to the scan flip-flop.
A test facilitating circuit for the integrated circuit as described. 3. A combination circuit or an analog block is arranged between two scan flip-flops or between a scan flip-flop and an input / output terminal, and the inverting circuit selects a scan signal according to the switching signal. After setting a test signal value in the scan flip-flop, an output signal of an inversion output terminal of the scan flip-flop is selected by the switching signal to invert the state value of the scan flip-flop. The output signal of the inverted output terminal of the flip-flop is selected to invert the state value of the scan flip-flop, and a start timing for transmitting the test signal value to the combinational circuit or the analog block is set. 2. The circuit for facilitating test of an integrated circuit according to 2. 4. The integrated circuit according to claim 3, wherein said scan flip-flop fetches an output value from a combinational circuit or an analog block after a lapse of a predetermined time from the start of propagation of the test value by said inverting circuit. Circuit for facilitating circuit test. 5. The integrated circuit test facilitation circuit according to claim 4, wherein a predetermined time from the test value propagation start timing is prepared for a plurality of different times each for a very short time. 6. An integrated circuit test facilitation circuit according to claim 5, wherein the output value from the combinational circuit or the analog block taken into the scan flip-flop is output to the outside via a scan line. 7. A test facilitation circuit for an integrated circuit having a boundary scan design and including an update flip-flop disposed around the outer periphery of a core circuit, wherein a state value of the update flip-flop is externally changed. A test facilitating circuit for an integrated circuit, comprising: an inverting circuit for inverting based on an input control signal. 8. The circuit for facilitating the test of an integrated circuit according to claim 1, wherein said core circuit is scan-designed and has a scan flip-flop therein. The circuit for facilitating test of an integrated circuit according to claim 7, wherein the circuit is configured. 9. The inverting circuit receives an output signal of an inverting output terminal of an update flip-flop and a scan signal, and outputs one of the two signals as a control signal input from the outside. 9. The integrated circuit test facilitation circuit according to claim 7, further comprising a switch selected by a switching signal and input to the update flip-flop. 10. A boundary lease scan is arranged around an outer periphery of a core circuit having a combinational circuit or an analog block, wherein the boundary lease scan has a shift flip-flop and the update flip-flop, The inverting circuit selects a scan signal that has passed through the shift flip-flop according to the switching signal and sets a test signal value in the update flip-flop, and then, according to the switching signal, an inverted output terminal of the update flip-flop. And inverts the state value of the update flip-flop.
Selecting an output signal of an inversion output terminal of the update flip-flop, inverting a state value of the update flip-flop, and setting a start timing for propagating the test signal value to the combinational circuit or the analog block. 9. The circuit for facilitating test of an integrated circuit according to claim 7, wherein: 11. The shift flip-flop according to claim 10, wherein an output value from a combinational circuit or an analog block is fetched after a lapse of a predetermined time from a timing of starting propagation of a test value by the inverting circuit.
A test facilitating circuit for the integrated circuit as described. 12. The circuit for facilitating test of an integrated circuit according to claim 11, wherein a predetermined time from the start timing of the propagation of the test value is prepared for a plurality of different times each for a very small time.