JP2002071761A - Circuit and method for delay test - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a circuit and a method, for a delay test, wherein a circuit to be delay-tested can be measured by a low-cost tester without increasing the chip area of an LSI. SOLUTION: The delay test circuit of a scan system is provided at the LSI, and it makes the delay test toy using the scan path circuit of the LSI. The delay test circuit is provided with a control means wherein a scan shift mode in which every scan flip-flop on a scan chain receives a clock signal and in which a scan input is retained and sent out is provided, a scan capture mode in which a data input is retained and sent out is provided and a scan flip-flop mode in which the output of the circuit to be delay-tested is received so as to be changed over independently of other scan flip-flops.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a delay test of a semiconductor device, and more particularly to a delay test circuit and a delay test method using a scan flip-flop of a logic integrated circuit.

[0002]

2. Description of the Related Art With the progress of integration technology, a huge number of logic circuits can be configured as a single device. However, on the other hand, high integration inevitably leads to deterioration of controllability and observability inside the logic integrated circuit,
This has been a problem in performing LSI tests. Then, L
As a design for facilitating the SI test, a scan path circuit is provided. That is, the flip-flop inside the circuit is connected to an unnecessary scan path circuit configuration during normal operation, and the circuit can be divided into combinational circuits by the scan flip-flop which is used as a control point or an observation point. Then, with respect to such a circuit, a test pattern is scanned into a scan chain, which is an additional connection form of a scan flip-flop, by a shift operation to perform a normal operation, and a test result is scanned out. The delay test using the scan path circuit can be tested not by the minimum cycle of the LSI test apparatus but by the minimum pulse generation interval. Usually, since the minimum pulse generation interval is smaller than the minimum cycle, there is a feature that measurement can be performed by an inexpensive tester that operates slower than an expensive high-speed tester that measures at a required speed.

Therefore, conventionally, a scan type delay test has been performed on the above-described logic integrated circuit. FIG.
11 is a circuit diagram of a conventional delay test circuit, in which scan flip-flops 10, 11, 12, 13, and 14 form a scan chain, and a combinational circuit 2 to be subjected to a delay test.
Perform a delay test on 1. In such a case, the delay test confirms that the delay between the scan flip-flop 11 and the scan flip-flop 12 is smaller than the test clock cycle. That is, in the case of FIG. 10, a test pattern which is a value to be set for performing a delay test is set on the scan flip-flops 10, 1 based on the logic of the combinational circuits 21, 22 and each scan flip-flop.
It is determined as a value of 1,12. Then, the value is set from the SIN terminal to the scan flip-flops 10, 11, and 12 by a scan shift using a scan path. Two clocks having a clock cycle width are input from the delay test clock terminal DCLK, and the change value of the scan flip-flop after the input of the two clocks is taken out by scan shift and confirmed by logic match / mismatch. In the prior art of FIG. 11, a NOT circuit 100, a selector circuit 101,
An OR circuit 102 and an inversion control signal are provided.

[0004]

However, the conventional delay test circuit and the conventional delay test method have the following problems. First, as a first problem, in the conventional delay test, the delay test target is the entire scan flip-flop under the same clock control, and the test clock cycle width is set between any scan flip-flops. Delay test failed. For example, in FIG. 10, the combination circuit 21 and the combination circuit 22 to be subjected to the delay test are logically independent, but the output of the combination circuit 21 or the scan flip-flop 1
In the case where the output of 1 is an input of the combinational circuit 22, the logic of the scan flip-flop 11 influences the determination of the output of the combinational circuit 22. It has been difficult to set a value (test pattern) for inverting the output of the combination target 21 and create an expected value. As a second problem, Japanese Patent Application Laid-Open No. H11-219385 provides a technique of "testing delay between arbitrary scan flip-flops", and a delay test between arbitrary scan flip-flops is not possible. However, as shown in FIG. 11, in addition to a conventional scan circuit, a NOT circuit 100, a selector circuit 101,
The OR circuit 102, the inversion control signal, and its wiring area are further added, which becomes an overhead. As a third problem, in JP-A-11-219385, a delay due to the capacitance of the NOT circuit 100 also occurs.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems in the prior art, and provides a delay test circuit and a delay test method capable of measuring a delay test target circuit with an inexpensive tester without increasing the chip area of an LSI. The purpose is to provide.

[Means for Solving the Problems]

A delay test circuit according to a first invention of the present application provided to solve the above-mentioned problem is a scan type delay test circuit provided in an LSI and performing a delay test using a scan path circuit of the LSI. In addition, a scan shift mode in which each scan flip-flop on the scan chain receives and receives a clock signal to hold and send a scan input and a scan capture mode in which data input is held and sent are provided. Control means is provided for enabling the mode of the scan flip-flop receiving the output to be switched independently of the other scan flip-flops.

[0007] By providing control means for switching the mode of the scan flip-flop receiving the output of the delay test target circuit independently of the other scan flip-flops, the delay test of the combinational circuit to be subjected to the delay test can be performed. Can be performed without being affected by the combinational circuit.

According to a second aspect of the present invention, there is provided a delay test circuit according to the first aspect of the present invention, wherein the control means switches a mode of the scan flip-flop. Control means for the signal, a terminal indicating that a delay test is being performed,
It is arranged before a mode switching signal input of a scan flip-flop that receives an output of the delay test target circuit, and comprises a combinational circuit to which the mode switching signal and a signal of a terminal indicating that the delay test is being performed are input. .

A delay test method according to a third aspect of the present invention, which is provided to solve the above-mentioned problem, includes a scan shift mode in which each scan flip-flop on a scan chain receives a clock signal and holds and transmits a scan input. A delay test method of a scan system for performing a delay test using a scan path circuit of an LSI having a scan capture mode for holding and transmitting data input, wherein after a test pattern is input, at least an input to a delay test target circuit is performed. A scan flip-flop is set to a scan shift mode, and at least a scan flip-flop receiving an output of a circuit to be tested for delay is set to a scan capture mode to collect a delay test.

A delay test is performed by setting only the scan flip-flop at the end of the path to be tested which receives the output of the circuit to be tested to scan capture mode.
A delay test of a combinational circuit to be subjected to a delay test can be performed without being affected by another combinational circuit.

A delay test method according to a fourth aspect of the present invention, which is provided to solve the above-mentioned problem, provides a scan in which a scan input of a scan flip-flop which is an input to a delay test target circuit receives an output of the delay test target circuit. The scan output of the flip-flop is connected.

A delay test method according to a fifth aspect of the present invention, which is provided to solve the above-mentioned problem, comprises: a scan shift mode in which each scan flip-flop receives a clock signal to hold and transmit a scan input; L having a scan capture mode for holding and sending
A scan type delay test method for performing a delay test using an SI scan path circuit, wherein after a test pattern is input, at least a scan flip-flop receiving an output of a delay test target circuit is set to a scan capture mode,
At least a can flip-flop which is an input of a delay test target circuit is set to a scan shift mode to perform a delay test.

According to a sixth aspect of the present invention, there is provided a delay test method according to the sixth aspect, wherein the scan flip-flop receiving the output of the delay test target circuit and the delay test target are provided. Using the values of at least three scan flip-flops including a scan flip-flop that is an input to the circuit and a scan flip-flop that is a scan input to the scan flip-flop that is an input to the delay test target circuit, a delay test pattern is formed. It is characterized in that it is created.

According to a seventh aspect of the present invention, there is provided a delay test method according to the fifth aspect of the present invention, wherein a scan input of a scan flip-flop to be input to a delay test target circuit is provided. Is connected to a scan output of a scan flip-flop that receives an output of the delay test target circuit, and at least a scan flip-flop that receives a delay test pattern output from the delay test target circuit and a scan flip-flop that becomes an input to the delay test circuit A delay test pattern is created using the value of the second scan flip-flop.

[0015]

(Embodiment 1) The configuration of a delay test circuit and a delay test method according to an embodiment of the present invention will be described below with reference to the drawings. FIG.
1 is a delay test circuit diagram illustrating a configuration of a delay test circuit and a delay test method according to an embodiment of the present invention. As shown in FIG. 1, the delay test circuit according to the present invention includes scan flip-flops 10, 11,
A combination circuit 20 is provided between the scan chain termination flip-flop 12 and the mode switching signal line 24, in addition to the scan path circuit including the mode switching signal lines 12, 13, 14, the mode switching signal line 24, and the clock signal line 23. are doing. The clock signal line 23 uses a system clock signal line, and CLK / SCK / DCLK are a normal clock terminal, a scan clock terminal, and a delay test clock terminal. Scan chains are generally known circuits,
And a clock input through a clock signal line 23, and a mode switching signal line 24 and an SMC signal.
It is possible to switch between a scan shift mode for inputting and outputting a test pattern and a test result using a scan path and a scan capture mode for performing a normal operation of the system. The combinational circuit 20 is for independently switching the mode of the flip-flop 12 receiving the output of the delay test target circuit, and has a terminal DTEST indicating that the delay test is being performed.
The terminal has a positive and negative logic under the input of the SMC signal and the DTEST signal.
It becomes a NOR circuit. In the first embodiment of the present invention, the DTE
The ST terminal is a terminal indicating that the delay test is being performed. The input / output terminals of the scan flip-flop on the scan path are called SIN terminal and SOUT terminal, respectively.
N and OUT are data input / output terminals of the flip-flop in the normal operation of the system.

The delay test circuit according to the present embodiment comprises a scan flip-flop 11 and a scan flip-flop 1.
2, there is a combinational circuit 21 which is a delay test target, and a combinational circuit 22 which can be a disturbance factor exists between the scan flip-flop 10 and the scan flip-flop 11.

Next, the operation of the delay test circuit and the delay test method according to an embodiment of the present invention will be described below with reference to FIGS. 1, 2, 3, 4, 5, and 6. . 2 and 6 are a delay test operation flowchart and a delay test timing chart showing the operation of the delay test circuit and the delay test method according to one embodiment of the present invention.
As shown in FIG. 2, in the delay test operation flow, in the scan shift-in step 150, a value (test pattern) to be set for performing a delay test by scan shift is set by the combination circuit 21 and the delay test target shown in FIG. The values of the scan flip-flops 11, 12, and 13 are obtained based on the logic of each scan flip-flop. Then, the value is sent from the SIN terminal to the scan flip-flops 11, 1
The scan shift using the scan path is set to 2 and 13. Next, in the delay test mode setting step 151, D
The scan flip-flop 11 can be in a scan shift mode, the scan flip-flop 12 can be in a scan capture mode, and the scan flip-flops 10, 13, and 14 can be in any mode. Next, in the delay test first clock input step 152, DCLK
The first clock is input to the terminal, and the value is propagated from the scan flip-flop 13 to the scan flip-flop 11 via the scan path in the scan shift mode,
A value is propagated from the scan flip-flop 11 to the scan flip-flop 12 via the combination circuit 21 to be tested in the scan capture mode. Next, in the delay test second clock input step 153, DCLK is changed from one clock of the delay test first clock input step 152 to a DCLK after a test clock cycle width which becomes a standard of the delay test.
A clock signal is input and propagated from the scan flip-flop 11 to the scan flip-flop 12 via the combination circuit 21 to be tested in the scan capture mode. Next, in a scan shift mode step 154,
The scan flip-flops 10, 11, 12, 13, and 14 are set to the scan shift mode by the DTEST terminal and the SMC terminal. Next, scan shift-out step 15
In step 5, values are sequentially output from the SOUT terminal by scan shift. Then, in a delay test determination step 156, the delay test target combinational circuit 21 and the scan flip-flop 11 are compared with expected values in consideration of the logic of the delay test target combinational circuit 21 prepared in advance and the logic matches / mismatches.
The path delay time between the scan flip-flop 12 and the scan flip-flop 12 is determined to be equal to or less than the cycle width of the clock (good) or equal to or more than (bad). still,
In the delay test mode setting step 151, the scan flip-flops 10, 13, and 14 may enter the scan capture mode when a delay test is performed on the path delay of another portion on the LSI at the same time.

Next, a description will be given of a case in which the delay of the rise of the path between the scan flip-flop 11 and the scan flip-flop 12 is tested by using the logical value. Here, the combinational circuit 21 to be subjected to the delay test is, for example, a buffer. First, the scan shift-in step 150 is performed so that the value of the scan flip-flop 12 changes from 0 to 1 in advance as a test pattern by two clock inputs to the DCLK terminal.
The scan flip-flop 11 is set to 0, the second scan flip-flop 12 is set to 1, and the third scan flip-flop 13 is set to 1 by scan shift (time ta shown in FIG. 6, FIG. 3). Next, delay test mode setting step 1
Reference numeral 51 denotes a DTEST terminal and an SMC terminal, so that the scan flip-flop 11 is in the scan shift mode, the scan flip-flop 12 is in the scan capture mode, and the scan flip-flops 10, 13, and 14 are in the scan shift mode (time t1 in FIG. 6). Next, in the delay test first clock input step 152, the first clock is input to the DCLK terminal (time tb in FIG. 6), and the first flip-flop 13 is transferred from the scan flip-flop 13 to the scan flip-flop 11 via the scan path in the scan shift mode. And propagate
0 is propagated from the scan flip-flop 11 to the scan flip-flop 12 via the combination circuit 21 to be tested in the scan capture mode (FIG. 4). Next, a delay test second clock input step 153
Then, a second clock is input to DCLK after a test clock cycle width from one clock in the delay test first clock input step 152 (time tc in FIG. 6), and 1 is set to the scan flip-flop 11.
To the scan flip-flop 12 in the scan capture mode via the combinational circuit 21 to be subjected to the delay test. Here, the value of the scan flip-flop 12 becomes 1 when the rising delay of the combinational circuit is equal to or smaller than the clock cycle width (good), and becomes 0 when the rising delay is equal to or larger than the clock cycle width (bad) (FIG. 5). Next, in the scan shift mode step 154, the scan flip-flops 10, 11, 12, 13, and 14 are set to the scan shift mode by the DTEST terminal and the SMC terminal (time t2 in FIG. 6). Next, the scan shift-out step 155 includes S in the scan shift.
The values are sequentially output from the OUT terminal. Finally, the delay test determination step 156 compares the logic value of the combination circuit 21 of the delay test target prepared in advance with the expected value in consideration of the logic, and determines whether the logic matches or mismatches the combinational circuit 21 of the delay test target and the scan flip-flop. Path delay time between the scan flip-flop 11 and the scan flip-flop 12 is equal to or less than the clock cycle width (good) /
The above (defective) is determined. (Time td in FIG. 6) In the first embodiment of the present invention, since the mode switching of the scan flip-flop 12 is enabled independently of other scan flip-flops, the mode of the scan flip-flop 11 is scanned throughout the delay test period. It is possible to set a shift mode. Therefore, as for the value of the scan flip-flop 11, the value previously set as the test pattern is reliably propagated from the scan flip-flop 13 located at the preceding stage on the scan chain, and is not affected by the combinational circuit 22.

(Embodiment 2) As another embodiment of the present invention, a case will be described in which the basic configuration is as described above, but two scan flip-flops are further controlled. FIG. 7 is a delay test circuit diagram showing a configuration of another embodiment of the delay test circuit and the delay test method according to the present invention. In the second embodiment of the present invention, as shown in FIG. 3, when the scan paths are connected by the scan rechain, the SOUT terminal of the scan flip-flop 12 receiving the output of the delay test target circuit is connected to the delay test target circuit. It is connected to the SIN terminal of the scan flip-flop 11 to be input. The scan flip-flop 12 also functions as the scan flip-flop 13 in the embodiment shown in FIG. The operation is as follows. In the scan shift-in step 150, a value to be set for performing a delay test is set on the scan flip-flop 1 based on the combinational circuit 21 to be tested and the logic of each scan flip-flop.
It is determined as a value of 1,12. Then, the value is set from the SIN terminal to the scan flip-flops 11 and 12 by scan shift using a scan path. Next, the delay test mode setting step 151 includes the DTEST terminal and the SM
With the C terminal, the scan flip-flop 11 is set to the scan shift mode, and the scan flip-flop 12 is set to the scan capture mode. Next, in a delay test first clock input step 152, the first clock is input to the DCLK terminal, and a value is propagated from the scan flip-flop 12 to the scan flip-flop 11 via the scan path in the scan shift mode, and In the scan capture mode, a value is propagated from the flip-flop 11 to the scan flip-flop 12 via the combinational circuit 21 to be subjected to the delay test. Next, the delay test second clock input step 153 includes the delay test first clock input step 1
DCLK after a test clock cycle width from one clock of 52
To the scan flip-flop 11
To the scan flip-flop 12 in the scan capture mode via the combinational circuit 21 to be subjected to the delay test. Next, a scan shift mode step 154 is performed.
Sets the scan flip-flop 12 to the scan shift mode by the DTEST terminal and the SMC terminal. Next, a scan shift out step 155 sequentially outputs values from the SOUT terminal by scan shift. Finally, the delay test determination step 156 compares the logic value of the combination circuit 21 to be prepared in advance with the expected value in consideration of the logic of the combination circuit 21 to be compared.
And a path delay time between the scan flip-flop 11 and the scan flip-flop 12 is equal to or less than a clock cycle width.
Judge (good) / more (bad).

Incidentally, the scan flip-flops 10, 13, and 14 in the delay test mode setting step 151 may be set to the scan capture mode when a path test of another part on the LSI is simultaneously performed with the delay test.

The second embodiment of the present invention has an effect that the delay test can be realized by two scan flip-flops. Therefore, when setting a value, the number of scan flip-flops to be set in consideration of logic is changed from three to two. Thus, test patterns can be created more easily than before.

(Embodiment 3) As another embodiment of the present invention, a case will be described in which a delay test of a plurality of combinational circuits becomes possible. FIG. 8 is a delay test circuit diagram showing a configuration of a delay test circuit and a delay test method according to the third embodiment of the present invention, which can perform a delay test of two combinational circuits at different positions. In the third embodiment of the present invention, as shown in FIG. 8, a delay test is performed on combinational circuits 23 and 21. Scan flip-flops 10 and 12, which receive outputs of the respective combinational circuits, are connected by combinational circuit 20. The mode can be set independently of other scan flip-flops. In Embodiment 3 of the present invention,
The combination circuit 23 is subjected to the delay test according to the first embodiment, and the combination circuit 21 is subjected to the delay test according to the second embodiment.
As in the third embodiment of the present invention, a plurality of scan flip-flops receiving outputs of combinational circuits at different positions are configured to be capable of independently setting a mode, so that a delay test of a plurality of combinational circuits can be performed by the same test. Delay tests can be performed at the same clock cycle or separately at different test clock cycles for each combinational circuit.

(Embodiment 4) As another embodiment of the present invention, a case will be described in which the mode of a scan flip-flop different from that of Embodiment 1 is independently switched to enable a delay test. FIG. 9 is a delay test circuit diagram showing a configuration of a delay test circuit and a delay test method according to a fourth embodiment of the present invention. In the present embodiment, as shown in FIG. 9, the difference from the first embodiment is that the combinational circuit 20a replaces the combinational circuit 20.
a is for independently switching the mode of the scan flip-flop 11 which is an input to the delay test target circuit.
EST and AND / OR / NAND / by positive logic / negative logic below the SMC signal and DTEST signal inputs.
It becomes a NOR circuit. The difference in operation from the first embodiment is that
When the TEST terminal is 1, the delay test is in progress. During the delay test,
The SMC terminal and the DTEST terminal set the scan flip-flops 10, 12, 13, and 14 to the scan capture mode, and set the scan flip-flop 11 to the scan shift mode.

[0024]

As described above, according to the delay test circuit and the delay test method according to the present invention, the delay test is performed by dividing the modes of the scan flip-flop 11 and the scan flip-flop 12 in FIG. A delay test can be performed regardless of the delay between scan flip-flops other than the target scan flip-flop. That is, as the first effect, the set value and the expected value of the delay test can be created without considering the combinational circuit 22 that is not the target of the delay test. As a second effect, FIG.
1, the NOT circuit 100, the selector circuit 101, and the OR circuit
The area overhead of the circuit 102 can be reduced. Further, as a third effect, a NOT circuit 100 is connected to the output of the scan flip-flop 11 through which logic propagates during normal operation.
Need not be connected, the operating speed does not deteriorate due to the capacity of the NOT circuit 100.

[Brief description of the drawings]

FIG. 1 is a delay test circuit diagram showing a configuration of a delay test circuit and a delay test method according to a first embodiment of the present invention.

FIG. 2 is a flowchart of a delay test operation in the first embodiment of the delay test circuit and the delay test method according to the present invention.

FIG. 3 is a delay test circuit diagram showing a logic state at a time ta in FIG. 6 according to the first embodiment of the present invention;

4 is a delay test circuit diagram showing a logic state at time tb in FIG. 6 according to the first embodiment of the present invention.

FIG. 5 is a delay test circuit diagram showing a logic state at time tc in FIG. 6 according to the first embodiment of the present invention.

FIG. 6 is a delay test timing chart in the first embodiment of the delay test circuit and the delay test method according to the present invention.

FIG. 7 is a delay test circuit diagram showing a configuration of a delay test circuit and a delay test method according to a second embodiment of the present invention.

FIG. 8 is a delay test circuit diagram showing a configuration of a delay test circuit and a delay test method according to a third embodiment of the present invention.

FIG. 9 is a delay test circuit diagram showing a configuration of a delay test circuit and a delay test method according to a fourth embodiment of the present invention.

FIG. 10 is a diagram of a delay test circuit according to the related art.

FIG. 11 is a circuit diagram of a delay test according to another related art.

[Explanation of symbols]

IN Input terminal for user circuit OUT Output terminal for user circuit SIN Scan shift-in terminal SOUT Scan shift-out terminal CLK Normal clock terminal SCK Scan clock terminal DCLK Delay test clock terminal SMC Switching between scan shift mode and scan capture mode DTEST During delay test Indicated terminal 10 Scan flip-flop 11 Scan flip-flop 12 Scan flip-flop Scan flip-flop receiving the output of the circuit to be tested for delay test 13 Scan flip-flop 14 Scan flip-flop 20 Combination circuit 20a Combination circuit 21 Combination circuit for delay test 22 Combination circuit 23 Clock signal line 24 Mode switching signal line 100 NOT circuit 101 Selector circuit 102 OR circuit 1 50 scan shift-in process 151 delay test mode setting process 152 delay test first clock input process 153 delay test second clock input process 154 scan shift mode setting process 155 scan shift out process 156 delay test determination process

 ──────────────────────────────────────────────────の Continued on the front page F term (reference) 2G032 AA01 AB01 AB06 AC10 AK16 AL00 5F038 DT01 DT02 DT03 DT04 DT05 DT06 DT07 DT10 DT15 DT17 EZ20

Claims (7)

[Claims] 1. A scan type delay test circuit provided in a semiconductor integrated circuit (hereinafter, referred to as an LSI) and performing a delay test using a scan path circuit of the LSI, wherein each scan flip-flop on a scan chain is provided. The flip-flop is provided with a scan shift mode for receiving and transmitting a scan signal in response to a clock signal, and a scan capture mode for retaining and transmitting a data input, and a mode of a scan flip-flop receiving an output of a delay test target circuit. A delay test circuit provided with control means for switching the scan flip-flop independently of other scan flip-flops. 2. A scan type delay test circuit provided in an LSI and performing a delay test using a scan path circuit of the LSI, wherein the scan type delay test circuit is provided for each scan on a scan chain. The flip-flop is provided with a scan shift mode in which a scan signal is held and transmitted in response to a clock signal, and a scan capture mode in which a data input is held and transmitted, and a mode of the scan flip-flop input to the delay test target circuit. A delay test circuit, which is provided with control means for enabling switching independently of other scan flip-flops. 3. The control means for a mode switching signal for switching a mode of the scan flip-flop, the control means being disposed at a terminal indicating that a delay test is being performed, and at a stage prior to a mode switching signal input of the controlled flip-flop. 3. The delay test circuit according to claim 1, comprising a combinational circuit to which the mode switching signal and a signal of a terminal indicating that the delay test is being performed are input. 4. A delay test method, wherein a scan output of a scan flip-flop receiving an output of the delay test target circuit is connected to a scan input of the scan flip-flop serving as an input to the delay test target circuit. 5. An LSI scan path circuit in which each scan flip-flop has a scan shift mode in which a scan signal is held and sent in response to a clock signal, and a scan capture mode in which a data input is held and sent. A scan type delay test method for performing a delay test, wherein after a test pattern is input, a scan flip-flop receiving at least an output of the delay test target circuit is set to a scan capture mode, and at least a scan flip-flop serving as an input of the delay test target circuit is A delay test method, wherein a delay test is performed in a scan shift mode. 6. A scan flip-flop receiving an output of a delay test target circuit, a scan flip-flop serving as an input to the delay test target circuit, and a scan flip-flop serving as a scan input to a scan flip-flop serving as an input to the delay test target circuit 6. The delay test method according to claim 5, wherein the delay test pattern is created using values of at least three scan flip-flops including the flip-flop. 7. A scan output of a scan flip-flop receiving an output of the delay test target circuit is connected to a scan input of the scan flip-flop serving as an input to the delay test target circuit, and a delay test pattern of the delay test target circuit is changed. 6. A delay test pattern according to claim 5, wherein a delay test pattern is created using values of at least two scan flip-flops of a scan flip-flop receiving an output and a scan flip-flop serving as an input to a delay test circuit. Method.