JP2003202362A - Circuit and method for scan test - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a scan test circuit in which the number of test pins required for a scan test of an LSI is reduced to a minimum and which reduces the testing time. <P>SOLUTION: The scan test circuit is provided with a shift register 11 and a shift register 12 which constitute two scan chains, to which a scan-in signal IN1, a scan clock CLK and a scan enable signal EN are supplied and which output a scan-out signal OUT1 and a scan-out signal OUT2, an inverter 2 which inverts the clock CLK and which outputs an inversed clock BCK, a selector 3 which responds to the supply of the enable signal EN, and selects one from among the clock CLK and the inversed clock BCK and which outputs a selected clock CKS so as to be supplied to the shift register 12, and a selector 41 which is synchronized with the clock CLK and which selects one from among the scan-out signals OUT1, OUT2 at the shift registers 11, 12 so as to be output as a scan-out signal SCO1. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a scan test circuit and a scan test method, and more particularly to a logic circuit LSI.
The present invention relates to a scan test circuit and a scan test method for testing a logic circuit of (semiconductor integrated circuit).

[0002]

2. Description of the Related Art Conventionally, in a logic circuit LSI, especially a combinational circuit, an L
It is widely used to have a scan test circuit, which is a circuit dedicated to the test, inside the SI, and confirm the normal operation of the combinational circuit by performing a test by the scan path method.

As is well known, this scan test circuit is composed of a scan path circuit chain in which scan path flip-flops are connected in series and operates as a shift register. This scan test circuit has a scan test input terminal for inputting a scan test signal which is scan test data (scan test pattern) from outside or inside the LSI, and a scan clock terminal for inputting a scan path test clock from outside the LSI. , And has a scan test output terminal for outputting scan test output data as a result of the scan test.

In the scan path system, in the test mode (shift mode), a scan test pattern for a test is input from the scan test input terminal (hereinafter referred to as scan-in), and a scan clock for a test is input to a clock terminal. By performing logical operation on the data by the combination circuit inside the LSI and confirming that the predetermined expected value as the operation result is output from the scan test output terminal as scan test output data (hereinafter, scan out), the combination circuit Is to confirm that it is operating normally. That is, if the scan test output data is in accordance with the expected value calculated in advance, it is determined that there is no defect in the combination circuit, and if it is not in accordance with the expected value, there is a manufacturing defect.

As described above, by adopting the scan test circuit, the inside of the circuit can be separated as a combination circuit, and the test becomes easy. In order to set and read data in the scan chain connected by scan connection, the number of clocks corresponding to the number of scan registers is required.
If only one scan chain is used, the number of clocks required for the test will increase. Therefore, by setting multiple scan chains, it is possible to set the data in the scan register and reduce the number of clocks required for reading. .
In addition, external terminals (pins) that need to be added for scan design include a test enable pin that separates test operation from normal operation, a scan-in pin that inputs scan data, and a scan-out pin that outputs scan data. The scan-in pin and the scan-out pin can be used also as the data input / output pin of the general logic circuit.

That is, as the number of scan chains increases, the number of flip-flops per scan chain, that is, the number of required clocks decreases, so that the time spent for scan-in / scan-out decreases and the test cost decreases.

However, the number of terminals (hereinafter referred to as pins) of the LSI is determined for each type of LSI, and therefore, the pins physically usable as scan-in pins / scan-out pins are limited. When the data input / output pins of a general logic circuit are also used as scan-in pins / scan-out pins, the general logic circuit is affected by the increase in delay time due to the addition of scan chains, etc., so the number of scan chains can be unconditionally increased. is not. Further, there are cases where the number of scan test data that can be input / output at the same time is limited due to the constraints of the tester. In recent years, semiconductor integrated circuits have become larger in scale, and the required test time has also increased. Therefore, reduction of test time is an important issue.

The conventional scan test circuit can be classified into the following two configuration methods from the viewpoint of the number of test pins and the number of test patterns.

The conventional first scan test circuit according to the first configuration method divides a scan chain constituting the scan test circuit into a plurality of parts, and provides a scan-in pin and a scan-out pin for each divided scan chain. Is.

For example, a conventional second scan test circuit according to the second construction method described in Japanese Patent Laid-Open No. 1-217278 is
In order to reduce the number of test pins, a scan control signal input pin is connected and a decoder that outputs a selection signal that selects one of the plurality of scan chains, and a plurality of scan chains corresponding to the selection signals that the decoder outputs are selected. A demultiplexer that inputs a single scan-in pin signal to any one of the shift registers, and outputs any one output of the shift register as a scan-out signal to a single scan-out pin according to the selection signal. And a multiplexer for use in the shift register, and one of the shift registers is sequentially selected by using the decoder, the demultiplexer, and the multiplexer.

Referring to FIG. 5, which shows a block diagram of a conventional first scan test circuit, the conventional first scan test circuit constitutes each scan chain divided into a plurality (three in this example) of lines. Scan-in signal IN1, I
A scan-in pin input to each of N2 and IN3, a scan clock pin input to the scan clock CLK,
A scan enable pin to which the scan enable signal EN is input and scan out signals OUT1, OUT2
Shift registers 51, 52, 53 each having a scan-out pin for outputting each of OUT3 are provided.

Next, the operation of the conventional first scan test circuit, that is, the conventional first scan test method will be described with reference to FIG. 5 and FIG. 6 showing the waveform of each signal in a time chart. First, at time T1, since the scan enable signal EN is “L”, the shift register 5 receives the scan clock CLK.
1, 52 and 53 do not work.

Next, at time T2, the scan enable signal EN becomes "H", and the scan operation is started. The data of each of the scan-in signals IN1, IN2, IN3 is A in synchronization with the rising edge of the scan clock CLK.
2, A3, A4 ..., B2, B3, B4 ... and C
2, C3, C4 ... Shift register 51
Reads the data A2, A3, A4 of the scan-in signal IN1, performs the shift operation internally, and outputs the corresponding scan result data D1, D2, D3 to the scan-out signal OU.
Output as T1. Similarly, the shift register 52
The data B2, B3, B4 of the scan-in signal IN2 is read, the shift operation is internally performed, and the scan result data E1, E2, E3 are output as the scan-out signal OUT2. Similarly, the shift register 53 reads the data C2, C3, C4 of the scan-in signal IN3, internally performs the shift operation, and scan result data F1, F
2 and F3 are output as the scan-out signal OUT3.

Referring to FIG. 7, which shows a block diagram of a conventional second scan test circuit, the conventional second scan test circuit constitutes each of a plurality (three in this example) of scan chains and scan-in. Signals IN1, IN2
A shift having a scan-in pin input by each of IN3, a scan clock pin input by a scan clock CLK, a scan control pin input by a scan enable signal EN, and a scan-out pin outputting each of scan-out signals SO1, SO2, SO3 A register 61, 62, 63 and a selection signal SL for decoding and selecting one of the shift registers 61, 62, 63 according to the supply of the scan control signal CS and a scan enable signal EN for the selected shift register are output. Decoder 64 and scan-in signal I according to selection signal SL
A demultiplexer 65 that selects and outputs one of N1, IN2, and IN3, and one of the scan-out signals SO1, SO2, and SO3 of the shift registers 61, 62, and 63 according to the selection signal SL. Selector 66 to output as scan-out signal SCO
With.

Next, the operation of the conventional second scan test circuit, that is, the conventional second scan test method will be described with reference to FIG. 7 and FIG. 8 showing the waveform of each signal in a time chart. First, at time T1,
Since the scan control signal CS is "0", the selection signal SL of the output of the decoder 65 and each scan enable signal EN1, EN2, EN3 are all "L", and the shift register 6 is supplied even if the scan clock CLK is supplied.
1, 62 and 63 do not work. For convenience of illustration,
In FIG. 7, scan enable signals EN1, EN2, EN
3 is indicated by one signal line.

Next, at time T2, the scan control signal CS
Becomes "1", and the decoder 65 sets only the scan enable signal EN1 of the shift register 61 to "H" to start the scan operation. At this time, the shift register 6
2, 63 scan enable signals EN2 and EN3 are "
The shift registers 62 and 63 do not operate because of L ". The data J1 of the scan-in signal IN1 is sent to the shift register 61 selected by the demultiplexer 65 in synchronization with the rising edge of the scan clock CLK. 61 reads the data J1, internally performs a shift operation, executes a logical operation, and outputs the corresponding scan result data P1 to the scan-out signal SO.
1 is supplied to the multiplexer 66. The multiplexer 66 outputs the scan-out signal SO1, that is, the scan result data P1 as the scan-out signal SCO.

When the shift register 61 has finished scanning with the data J1 of the scan-in signal IN1, the scan control signal CS becomes "2", and the decoder 65 outputs only the scan enable signal EN2 of the shift register 62.
The scan operation is started as "H". At this time, the scan enable signal EN for the shift registers 61 and 63 is set.
1 and EN3 are "L", so these shift registers 6
1,63 do not work. The data K1 of the scan-in signal IN2 is sent to the shift register 62 selected by the demultiplexer 65 in synchronization with the rising edge of the scan clock CLK. The shift register 62 stores data K
1 is read, the shift operation and the logical operation are executed internally,
The corresponding scan result data Q1 is transferred to the multiplexer 66.
Supply to. The multiplexer 66 outputs the scan-out signal SO2, that is, the scan result data Q1 as the scan-out signal SCO.

When the shift register 62 finishes scanning with the data K1 of the scan-in signal IN2, the scan control signal CS becomes "3", and the decoder 65 outputs only the scan enable signal EN3 of the shift register 63.
The scan operation is started as "H". At this time, the shift registers 61 and 62 do not operate in response to "L" of the scan enable signals EN1 and EN2. Scan-in is performed in synchronization with the rising edge of the scan clock CLK. The data L1 of the signal IN3 is the demultiplexer 6
It is sent to the shift register 63 selected in 5. The shift register 63 reads the data L1, internally executes a shift operation / logical operation, and supplies the corresponding scan result data R1 to the multiplexer 66. The multiplexer 66 outputs the scan-out signal SO3, that is, the scan result data R1 as the scan-out signal SCO.

When the shift register 63 finishes scanning with the data L1 of the scan-in signal IN3, the scan control signal CS becomes "1", and the decoder 65 outputs only the scan enable signal EN1 of the shift register 61.
H "is set to start the scanning operation.

The above operation is repeated.

Although the first conventional scan test circuit can reduce the number of test patterns, it requires a scan-in pin and a scan-out pin for each of a plurality of shift registers, so that the number of shift registers, that is, scan chains is required. There is a problem that the number of required test pins increases as the number increases.

Although the second conventional scan test circuit can reduce the number of test pins, the test is performed for each selected shift register. Therefore, the same test is repeated the same number of times as the number of shift registers. You have to do
It is not possible to test all the shift registers, that is, the scan chains at the same time, and as a result, it takes the same test time as when testing all the shift registers by connecting them in series as one scan chain. Had.

[0023]

Although the above-described first conventional scan test circuit and scan test method can reduce the number of test patterns, a scan-in pin and a scan-out pin are required for each of a plurality of shift registers. Therefore, there is a drawback that the number of required test pins increases as the number of shift registers, that is, the number of scan chains increases.

Further, although the second conventional scan test circuit can reduce the number of test pins, it is necessary to perform a test for each selected shift register. Therefore, the same test is performed the same number of times as the number of shift registers. It is necessary to perform iteratively, and it is not possible to test all the shift registers, that is, the scan chains at the same time. In the end, the same test as when all the shift registers are connected in series as one scan chain. It had the drawback of taking time.

The object of the present invention is to solve the above drawbacks and
An object of the present invention is to provide a scan test circuit and a scan test method capable of minimizing the number of test pins required for the I scan test and reducing the test time.

[0026]

According to a first aspect of the present invention, a scan test circuit is constituted by a series connection circuit of a plurality of flip-flops for testing an internal circuit of an LSI composed of a logic circuit and operates as a shift register. A scan chain is provided, scan test data and a scan clock for test are input in the test mode, the internal circuit performs a logical operation, and the internal circuit operates normally based on the scan-out result data which is the output of the operation result. In a scan test circuit that performs a scan path test to confirm that the first shift register operates in synchronization with the first edge of the scan clock, and the first shift register operates in synchronization with the second edge of the scan clock. A second shift register that operates as follows,
An output switching unit that switches the first and second scan-out data output from each of the first and second shift registers and outputs the scan-out result data is configured.

According to a second aspect of the present invention, in the scan test circuit according to the first aspect, the first edge is a rising edge and the second edge is a falling edge. It is a thing.

According to a third aspect of the present invention, in the scan test circuit according to the first aspect, an inverter that inverts the scan clock and outputs an inverted clock, and a scan that activates the scan test circuit in the test mode. A clock selector that selects one of the scan clock and the inverted clock in response to the supply of the enable signal, outputs the selected clock, and supplies the selected clock to the second shift register.

A scan test circuit according to a fourth aspect of the present invention includes a scan chain configured by a series connection circuit of a plurality of flip-flops for testing an internal circuit of an LSI composed of a logic circuit and operating as a shift register. In the mode, scan test data for a test and a scan clock are input, logical operation is performed by the internal circuit, and it is confirmed that the internal circuit is operating normally based on the scan-out result data which is the output of the operation result. In a scan test circuit that performs a campus-type test, each of the first and second scan chains is configured to include a scan-in pin to which a scan-in signal is input, a scan-clock pin to which the scan clock is input, and a scan-time pin during the test mode. Activate scan test circuit First and second shift registers each having a scan enable pin for inputting a scan enable signal and a scan out pin for outputting each of the first and second scan out signals, and an inversion clock by inverting the scan clock. An inverter for outputting and a scan clock pin of the second shift register for selecting one of the scan clock and the inverted clock in response to the supply of the scan enable signal in the test mode and outputting a selected clock. A clock input switching selector to be supplied to the first and second scan registers, and the scan out by selecting one of the first and second scan out signals of each of the first and second shift registers in synchronization with the scan clock. Output switching select output as result data And it is configured to include and.

According to a fifth aspect of the present invention, in the scan test circuit according to the fourth aspect, the clock input switching selector sets the scan clock to the second level when the scan enable signal is at the first level. When the scan clock is at the second level, the output switching selector outputs the first scan-out signal when the scan clock is at the second level, and when the scan clock is at the second level, the inversion clock is output as the selection clock. Each of the two scan-out signals is output as the scan-out result data.

According to a sixth aspect of the present invention, in the scan test circuit according to the fourth aspect, each of the first and second shift registers is a latch that holds 1-bit data. (Positive integer) bit shift register, n flip-flops, m (positive integer) internal circuits to be scan tested, and the scan clock when the scan enable signal is at the active level. Clock mask means for supplying the shift clock of the shift clock and stopping the supply of the shift clock by masking the scan clock when it is in the inactive level.

According to a seventh aspect of the present invention, in the scan test circuit according to the fourth aspect, the clock mask means includes an AND circuit which outputs a logical product of the scan enable signal and the scan clock. Has been done.

A scan test circuit according to an eighth aspect of the present invention includes a scan chain configured by a series connection circuit of a plurality of flip-flops for testing an internal circuit of an LSI composed of a logic circuit, the scan chain operating as a shift register, and a test. In the mode, scan test data and a scan clock for test are input, logical operation is performed by the internal circuit, and it is confirmed that the internal circuit is operating normally based on the scan-out result data which is the output of the operation result. In a scan test circuit that performs a scan path method test, each of a first scan chain and a second scan chain is formed, and a scan-in pin to which a first scan-in signal is input, and a scan-clock pin to which the scan clock is input, The scan test circuit is activated in the test mode. A first and a second shift register respectively having a scan enable pin for inputting a scan enable signal to be converted and a scan out pin for outputting each of the first and second scan out signals, and the third and fourth scan chains. A scan-in pin that constitutes each of the above, a scan-in pin to which a second scan-in signal is input, and a scan clock pin to which the scan clock is input,
Third and fourth shift registers each having a scan enable pin for receiving a scan enable signal for activating a scan test circuit in the test mode and a scan out pin for outputting each of the second and third scan out signals; An inverter that inverts the scan clock and outputs an inverted clock; and, in response to the supply of the scan enable signal in the test mode, selects one of the scan clock and the inverted clock and outputs the selected clock. Second and fourth
A clock input switching selector supplied to the scan clock pin of the shift register, and one of the first and second scan out signals of each of the first and second shift registers in synchronization with the scan clock. A first output switching selector that selects one and outputs it as first scan-out result data, and the third and fourth shift registers of the third and fourth shift registers in synchronization with the scan clock. A second output switching selector that selects one of the scan-out signals and outputs it as second scan-out result data is configured.

According to a ninth aspect of the present invention, there is provided a scan test method comprising a scan chain constituted by a series connection circuit of a plurality of flip-flops for testing an internal circuit of an LSI composed of a logic circuit, the scan chain being operated as a shift register. At the same time, a scan path for inputting scan test data and a scan clock for testing, causing the internal circuit to perform a logical operation, and confirming that the internal circuit is operating normally based on the scan-out result data that is the output of the operation result. In the test method of the method,
The first shift register is operated in synchronization with the first edge of the scan clock, and the second shift register is operated in synchronization with the second edge of the scan clock. The first and second scan-out data output from each shift register are switched to output the scan-out result data.

Further, the invention according to claim 10 is the invention according to claim 9.
In the scan test method described above, the first edge is a rising edge and the second edge is a falling edge.

[0036]

BEST MODE FOR CARRYING OUT THE INVENTION Next, embodiments of the present invention will be described in detail with reference to the drawings.

The scan test circuit and the scan test method according to the present embodiment are provided with a scan chain composed of a series connection circuit of a plurality of flip-flops for testing an internal circuit of an LSI composed of a logic circuit and operating as a shift register. In the test mode, input the scan test data and scan clock for the test, logically operate by the above internal circuit, and confirm that the internal circuit is operating normally based on the scan out result data which is the output of the operation result. In a scan test circuit for performing a scan path method test, a first shift register that operates in synchronization with a first (rising) edge of the scan clock, and a second (falling) edge of the scan clock. Second that operates in synchronization with
And the output switching means for switching the first and second scan-out data output from each of the first and second shift registers to output the scan-out result data. Both the rising edge and the falling edge of
And two scan chains, which are the second shift register, are simultaneously operated.

Next, referring to FIG. 1 which is a block diagram showing a first embodiment of the present invention, the scan test circuit of the present embodiment shown in this figure constitutes two scan chains and scan-in is performed. The scan-in pin input by the signal IN1, the scan-clock pin input by the scan-clock CLK, the scan-enable pin input by the scan-enable signal EN for activating the scan-test circuit in the test mode, and the scan-out signal OUT
Shift registers 11 and 12 each having a scan-out pin that outputs 1 and OUT2, an inverter 2 that inverts the scan clock CLK and outputs an inverted clock BCK, and a scan clock in response to the supply of the scan enable signal EN. CLK and inverted clock BCK
And a selector 3 for switching the clock input for outputting the selected clock CKS to output the selected clock CKS to the scan clock pin of the shift register 12, and the scan out of each of the shift registers 11 and 12 in synchronization with the scan clock CLK. An output switching selector 41 that selects one of the signals OUT1 and OUT2 and outputs it as a scan-out signal SCO1 is provided.

In this embodiment, the selector 3 for switching the clock input of the shift register 12 uses the scan clock CLK when the scan enable signal EN is "L".
When it is "H", the inverted clock BCK is output as the selected clock CKS. Further, the output switching selector 41 outputs the scan-out signal OUT1 as the scan-out signal SCO1 when the scan clock CLK is “H” and outputs the scan-out signal OUT2 when the scan clock CLK is “L”.

Referring to FIG. 2, which shows in block form an example of the structure of the shift register 11 on behalf of the shift registers 11 and 12, the shift register 11 shown in this figure has latches (flip-flops) each holding 1-bit data. , 11n that constitute a shift register of n (positive integer) bits and m (positive integer) internal circuits 121 to be scan tested.
122, ..., 12 m and scan enable signal E
The AND circuit 131 outputs a logical product of N and the scan clock CLK as the shift clock CK.

The AND circuit 131 keeps the scan clock CLK while the scan enable signal EN is "L".
Are masked so that the shift register 11 does not operate.

Each of the F / Fs 111, 112, ..., 11n holds the value of the input D at the rising edge of the shift clock CK and outputs the held value from the output Q.

Internal circuits 121, 122, ..., 12 m
Each is a logic circuit based on the specifications of the system, and is a black box here, but outputs a unique result according to the state of the input.

Next, the operation of the present embodiment, that is, the scan test method of the present embodiment will be described with reference to FIGS. 1 and 2 and FIG. 3 showing the waveform of each signal in a time chart. First, at time T1 Since the scan enable signal EN is “L”, the scan clock CLK
Is supplied, the AND circuit 131 stops supplying the shift clock CK.
12 does not work.

Next, at time T3, the scan enable signal EN becomes "H", the AND circuit 131 of the shift register 11 changes from the supply stop state of the shift clock CK to the supply state, and the supply of the shift clock CK1 is started. The shift register 11 starts the scan operation. At the same time, the selector 3 uses the inverted clock BCK obtained by inverting the inverter 2 as the scan clock and shift register 1
Supply to 2.

In synchronization with the timing of the rising edge of the scan clock CLK, the scan-in signal IN1 is the data S2, S when the scan clock CLK is "H".
3, S4 ..., On the other hand, in synchronization with the timing of the falling edge, the scan-in signal IN1 is data U2, U3, U when the scan clock CLK is "L".
It changes to 4. Since the shift register 11 is synchronized with the rising edge, the scan-in signal IN1
Data S2, S3, S4 of the above are read, a shift operation is internally performed, a logical operation is executed, and corresponding scan result data T1, T2, T3 is supplied to the selector 41 as a scan out signal OUT1.

Similarly, since the shift register 12 is synchronized with the falling edge, the data U2, U3, U4 of the scan-in signal IN1 is read, the shift operation is internally performed, the logical operation is performed, and the corresponding scan is performed. The result data V1, V2, V3 are supplied to the selector 41 as the scan-out signal OUT2.

As described above, the shift register 11 and the shift register 12 output different results at different terminals (pins).
Of the scan-out signal OU
At the falling edge of T1, the scan-out signal OUT2 is output as the scan-out signal SCO1.

As described above, in the scan test circuit and the scan test method of the present embodiment, if the number of terminals that can be used as scan-in pins / scan-out pins is the same, the number of scan chains is substantially doubled. Therefore, if the number of terminals and the clock frequency are the same, the test time can be reduced to half.

Next, referring to FIG. 4 which is a block diagram showing the second embodiment of the present invention, the difference between the first embodiment shown in this figure and the first embodiment is that the first embodiment is different from the first embodiment. That is, three sets of scan test circuits according to the embodiment are provided, and the number of scan chains is tripled, that is, six. That is, the shift registers 11 and 12 of the first embodiment
In addition to the AND circuit 2, the selector 3, and the selector 41, the shift registers 13 and 14 that output the scan-out signals OUT3 and OUT4 in response to the supply of the scan-in signal IN2, and the supply of the scan-in signal IN3 Corresponding to the shift registers 15 and 16 for outputting the scan-out signals OUT5 and OUT6, respectively, and one of the scan-out signals OUT3 and OUT4 of the shift registers 13 and 14 is selected in synchronization with the scan clock CLK. An output switching selector 42 that outputs the scan-out signal SCO2, and a scan clock CL
The output switching selector 43 selects one of the scan-out signals OUT5 and OUT6 of the shift registers 15 and 16 in synchronization with K and outputs it as the scan-out signal SCO3.

The operation of the present embodiment is similar to that of the first embodiment, in addition to the operations related to the shift registers 11 and 12, a set of shift registers 13 and 14 and a set of shift registers 15 and 16 are provided. Scan-in signal IN
Scanout signal S in response to supply of 2 and IN3
The operation is the same as that of the first embodiment except that the operation of outputting each of CO2 and SCO3 is performed in parallel.

As described in the prior art, the time required for the scan test is shorter when the shift registers constituting the scan chain are divided into a plurality of parts and each divided shift register is scanned.

In the present embodiment, as described above, three sets of scan test circuits according to the first embodiment are provided and the number of shift registers is six. However, this number is arbitrary depending on the number of usable terminals. Obviously it can be set to.

[0054]

As described above, according to the scan test circuit and the scan test method of the present invention, the first shift register that operates in synchronization with the first edge of the scan clock and the second shift register of the scan clock are used. A second shift register that operates in synchronization with an edge, and the first and second shift registers
Output switching means for switching the first and second scan-out data output from each shift register and outputting the scan-out result data, and two different ones at the rising edge and the falling edge of the scan clock. Since the shift register that configures the scan chain is operated, the number of scan chains can be virtually doubled if the number of pins that can be used as scan-in pins / scan-out pins is the same, and therefore the number of pins and the clock frequency are equal. Then, there is an effect that the test time can be reduced to half.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of a scan test circuit of the present invention.

FIG. 2 is a block diagram showing an example of a configuration of the shift register in FIG.

FIG. 3 is a time chart showing the operation of the scan test circuit of the present embodiment, which is the scan test method of the present embodiment.

FIG. 4 is a block diagram showing a second embodiment of the scan test circuit of the present invention.

FIG. 5 is a block diagram showing an example of a conventional first scan test circuit.

FIG. 6 is a time chart showing an example of a conventional first scan test method which is an operation of the conventional first scan test circuit.

FIG. 7 is a block diagram showing an example of a conventional second scan test circuit.

FIG. 8 is a time chart showing an example of a conventional second scan test method which is an operation of the conventional second scan test circuit.

[Explanation of symbols]

2 Inverters 3, 41, 42, 43 Selectors 11, 12, 13, 14, 15, 16, 51, 52, 5
3, 61, 62, 63 shift register 64 decoder 65 demultiplexer 66 multiplexers 111, 112, ..., 11n F / F 121, 122, ..., 12m Internal circuit 131 AND circuit

Claims (10)

[Claims] 1. A scan chain comprising a series connection circuit of a plurality of flip-flops for testing an internal circuit of an LSI composed of a logic circuit and operating as a shift register, comprising scan test data and a scan for a test in a test mode. A scan test circuit that inputs a clock, causes the internal circuit to perform a logical operation, and performs a scan-path test to confirm that the internal circuit is operating normally based on the scan-out result data that is the output of the operation result. A first shift register that operates in synchronization with a first edge of the scan clock; a second shift register that operates in synchronization with a second edge of the scan clock; First and second scans, each output of the second shift register A scan test circuit comprising: output switching means for switching out data and outputting the scan out result data. 2. The scan test circuit according to claim 1, wherein the first edge is a rising edge and the second edge is a falling edge. 3. An inverter that inverts the scan clock and outputs an inverted clock, and one of the scan clock and the inversion clock in response to supply of a scan enable signal that activates a scan test circuit in the test mode. 2. The scan test circuit according to claim 1, further comprising a clock selector that selects one of them, outputs a selected clock and supplies the selected clock to the second shift register. 4. A scan test data and scan for a test in a test mode, comprising a scan chain composed of a series connection circuit of a plurality of flip-flops for testing an internal circuit of an LSI composed of a logic circuit and operating as a shift register. A scan test circuit that inputs a clock, causes the internal circuit to perform a logical operation, and performs a scan-path test to confirm that the internal circuit is operating normally based on the scan-out result data that is the output of the operation result. In, each of the first and second scan chains, a scan-in pin to which a scan-in signal is input, a scan clock pin to which the scan clock is input, and a scan enable signal for activating a scan test circuit in the test mode Enter Catcher emission enable pin and the first and second each having a scan-out pin for outputting each of the first and second scan-out signal
Shift register, an inverter that inverts the scan clock and outputs an inverted clock, and selects and selects one of the scan clock and the inverted clock in response to the supply of the scan enable signal in the test mode. A clock input switching selector that outputs a clock and supplies the clock to the scan clock pin of the second shift register; and the first and second selectors of each of the first and second shift registers in synchronization with the scan clock. An output switching selector that selects one of the scan-out signals and outputs it as the scan-out result data. 5. The clock input switching selector outputs the scan clock as the selection clock when the scan enable signal is at a first level, and outputs the inversion clock as the selection clock when the scan enable signal is at a second level. The switching selector outputs the first scan-out signal as the scan-out result data when the scan clock is at the second level, and outputs the second scan-out signal when the scan clock is at the first level. The scan test circuit according to claim 4. 6. Each of the first and second shift registers is a latch that holds 1-bit data, and n flip-flops that form an n (positive integer) bit shift register, M (a positive integer) number of the internal circuits to be scan-tested, the scan clock is supplied as a shift clock of the flip-flop when the scan enable signal is at the active level, and the scan clock is masked when the level is inactive. 5. The scan test circuit according to claim 4, further comprising clock mask means for stopping the supply of the shift clock. 7. The clock mask means includes an AND circuit that outputs a logical product of the scan enable signal and the scan clock.
The described scan test circuit. 8. A scan chain, which comprises a series connection circuit of a plurality of flip-flops for testing an internal circuit of an LSI composed of a logic circuit and operates as a shift register, comprises scan test data for testing and a scan test data in a test mode. A scan test in which a scan clock is input, a logical operation is performed by the internal circuit, and a scan path method test is performed to confirm that the internal circuit is operating normally based on the scan-out result data that is the output of the operation result. In the circuit, each of the first and second scan chains is configured to
Of the scan-in signal, the scan-clock pin input by the scan clock, the scan-enable pin input by the scan-enable signal for activating the scan test circuit in the test mode, and the first and second scan-out signals. First and second shift registers each having a scan-out pin for outputting each, and each of a third and a fourth scan chain,
Of the scan-in signal, the scan-clock pin of the scan clock, the scan-enable pin of the scan-enable signal for activating the scan test circuit in the test mode, and the second and third scan-out signals. And a scan-out pin for outputting each of the
And a fourth shift register, an inverter that inverts the scan clock and outputs the inverted clock, and one of the scan clock and the inverted clock in response to the supply of the scan enable signal in the test mode. A clock input switching selector that outputs a selected clock and outputs the selected clock to the scan clock pins of the second and fourth shift registers; and each of the first and second shift registers in synchronization with the scan clock. A first output switching selector that selects one of the first and second scan-out signals and outputs it as first scan-out result data; and the third and fourth selectors in synchronization with the scan clock. Any one of the third and fourth scan-out signals of each shift register And a second output switching selector that outputs the second scan-out result data. 9. A scan test data and a scan for a test in a test mode, comprising a scan chain composed of a series connection circuit of a plurality of flip-flops for testing an internal circuit of an LSI composed of a logic circuit and operating as a shift register. A scan path test method for inputting a clock, performing a logical operation by the internal circuit, and confirming that the internal circuit is operating normally based on the scan-out result data that is the output of the operation result, wherein the scan clock The first shift register is operated in synchronization with a first edge of the scan clock, the second shift register is operated in synchronization with a second edge of the scan clock, and the first and second shift registers are operated. The first and second scan-out data, which are the outputs of the A scan test method characterized by outputting scan-out result data. 10. The scan test method according to claim 9, wherein the first edge is a rising edge and the second edge is a falling edge.