JP4215860B2 - Timing pulse generation circuit and semiconductor test apparatus - Google Patents

Timing pulse generation circuit and semiconductor test apparatus Download PDF

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Publication number
JP4215860B2
JP4215860B2 JP15568598A JP15568598A JP4215860B2 JP 4215860 B2 JP4215860 B2 JP 4215860B2 JP 15568598 A JP15568598 A JP 15568598A JP 15568598 A JP15568598 A JP 15568598A JP 4215860 B2 JP4215860 B2 JP 4215860B2
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Prior art keywords
timing
signal
timing pulse
interleave
means
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JPH11352198A (en
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勝 杉本
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株式会社ルネサステクノロジ
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Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a timing pulse generation circuit and a semiconductor test apparatus, and more particularly to a timing pulse generation circuit suitable for executing various tests for LSIs, and a semiconductor test apparatus using the timing pulse generation circuit About.
[0002]
[Prior art]
  2. Description of the Related Art Conventionally, semiconductor test apparatuses that perform various tests using an LSI as a device to be measured are known.FIG.These show the circuit diagram of the timing pulse generation circuit with which the conventional semiconductor testing apparatus is provided.
  The conventional timing pulse generation circuit includes a reference signal generation unit 3. The reference signal generator 3 is a part that generates an internal reference signal of the semiconductor test apparatus. In the semiconductor test apparatus, the execution cycle of the processing cycle is determined based on the reference signal.
[0003]
The reference signal generator 3 is connected to a plurality of timing generators (TGs), more specifically, first to nth TGs, that is, n TGs. The first to nth TGs include a first to nth counter 1 and a first to nth vernier 2, respectively. The first to n-th counters 1 are supplied with the reference signal generated by the reference signal generator 3. On the other hand, the first to n-th vernier 2 is supplied with a reference signal subjected to a predetermined delay process (hereinafter referred to as a delayed reference signal) and an output signal of the first to n-th counter 1.
[0004]
The first to n-th counters 1 increment the count value based on the reference signal and reset the count value every cycle. Further, each of the first to n-th counters 1 can read a user's setting every cycle and generate a timing pulse when the count value becomes a value corresponding to the setting. According to the 1st thru | or the nth counter 1, the rough timing pulse according to a user's setting can each be produced | generated by performing said process.
[0005]
The first to n-th vernier 2 takes OR logic between the output pulse of the first to n-th counter 1 and the delay reference signal, and generates a desired timing pulse based on the obtained signal. Each of the first to n-th verniers 2 can read a user's setting every cycle and generate a timing pulse so that an edge that exactly matches the setting can be obtained. According to the 1st thru | or the nth vernier 2, by performing said process, each can generate the timing pulse corresponding to a user's setting correctly.
[0006]
The first to nth vernier outputs, that is, the first to nth TG outputs are supplied to the waveform forming circuit 4. The waveform forming circuit 4 is provided corresponding to one output pin. The waveform forming circuit 4 is a circuit that inverts the pin output every time a timing pulse is supplied from any of the first to n-th TGs. In the timing pulse generation circuit shown in FIG. 15, the waveform supply circuit 4 can be supplied with n timing pulses from the first to nth TGs in one cycle. Therefore, the timing pulse generation circuit shown in FIG. 15 can generate n timing pulses in one cycle.
[0007]
The timing pulse output from the waveform forming circuit 4 is supplied to one pin of the device under measurement or to a determination circuit built in the semiconductor test apparatus. When the timing pulse is supplied to pin 1 of the device under measurement, for example, it is used as an address signal or a clock signal. On the other hand, when the timing pulse is supplied to the determination circuit, it is used as a signal for determining the timing for determining the output of the device under measurement.
[0008]
A semiconductor test apparatus may be required to change the timing pulse generation time in real time according to the content of the test to be executed. According to the semiconductor test apparatus shown in FIG. 15, the timing pulse generation timing is changed in real time by changing the commands to the first to n-th counter 1 and the first to n-th vernier 2, that is, the setting by the user. be able to.
[0009]
By the way, in the conventional semiconductor test apparatus, the first to n-th counter 1 and the first to n-th vernier 2 read a user's setting every cycle and generate timing pulses at a timing according to the setting. . For this reason, the first to nth TGs are in a state in which timing pulses cannot be generated while the setting of timing data and the like is completed after one cycle is started.
[0010]
FIG. 16 shows the relationship between the period in which the above state occurs (hereinafter referred to as a timing dead zone) and the cycle of the processing cycle in the semiconductor test apparatus. In the conventional semiconductor test apparatus, the period indicated by hatching in FIG. 16 is a timing dead zone in all of the first to nth TGs.
[0011]
When the semiconductor test apparatus is required to generate a timing pulse at high speed, generation of a timing pulse is required for the same TG immediately before the end of the cycle N and immediately after the start of the cycle N + 1. Things can happen. That is, after the timing pulse indicated by the solid line in FIG. 16, a situation may be required in which the generation of the timing pulse indicated by the broken line is required.
[0012]
However, when it is required to change the generation timing of the pulse in real time with the generation of the pulse at the timing described above, the timing at which the latter pulse, that is, the pulse indicated by the wavy line should be generated is the timing dead zone. Inside. Therefore, the conventional semiconductor test apparatus shown in FIG. 15 cannot generate a desired timing pulse under such a situation.
[0013]
FIG. 17 shows a circuit diagram of a timing pulse generation circuit conventionally used for solving the problem of the timing dead zone. The timing pulse generation circuit shown in FIG. 17 includes first to m + 1th TGs (m is an odd number). Each of the first to m + 1th TGs includes a first to m + 1th counter 1 and a first to m + 1th vernier 2.
[0014]
An enable circuit 5 is provided for each of the first to m + 1th TGs. The enable circuit 5 is a circuit that selectively enables or disables an input to the TG. In the timing pulse generation circuit shown in FIG. 17, the reference signal generation unit 3 outputs a change signal that is inverted every processing cycle.
[0015]
The change signal is directly supplied to the enable circuit 5 included in the even-numbered TG among the first to m + 1th TGs. On the other hand, the change signal is supplied via the inverter circuit to the enable circuit 5 included in the odd-numbered TG among the first to m + 1th TGs. According to the above-described structure, the even-numbered TG group and the odd-numbered TG group are alternately enabled every processing cycle of the semiconductor test apparatus.
[0016]
The first to m + 1th TGs are provided with one interleave circuit 6 for every two adjacent TGs. The interleave circuit 6 is a circuit that validates the output of one of the two TGs for each period. According to said structure, the timing pulse produced | generated by the even-numbered TG and the timing pulse produced | generated by the odd-numbered TG can be alternately output from the interleave circuit 6 for every period of a processing cycle. .
[0017]
That is, in the timing pulse generation circuit shown in FIG. 17, during the period in which even-numbered TGs generate timing pulses, the processing for generating odd-numbered TGs in the next period can be terminated. . Similarly, during the period in which the odd-numbered TGs generate timing pulses, the processing for generating even-numbered TGs in the next period can be terminated. Therefore, according to the timing pulse generation circuit shown in FIG. 17, it is possible to reliably prevent a timing dead zone from occurring immediately after the start of each cycle.
[0018]
[Problems to be solved by the invention]
However, according to the configuration of the timing pulse generation circuit shown in FIG. 17, TG twice as much as the maximum number of timing pulses that can be generated in one cycle is required. That is, according to the configuration shown in FIG. 15, the function of generating n timing pulses in one cycle can be realized by n TGs, whereas according to the configuration shown in FIG. Using m + 1 TGs, only m + 1/2 timing pulses can be generated in one cycle. For this reason, the conventional timing pulse generation circuit shown in FIG. 17 is likely to cause inconveniences such as an increase in power consumption and an increase in board size, an increase in size of the apparatus, and an increase in cost due to an increase in mounting parts. It was.
[0019]
The present invention has been made to solve the above-described problems, and includes one waveform forming circuit and a plurality of TGs for each pin, and all TGs can generate timing pulses within one cycle. It is a first object of the present invention to provide a timing pulse generation circuit that realizes both a state and a state in which generation of a timing dead zone is prevented by interleaving some TGs with other TGs.
[0020]
A second object of the present invention is to provide a semiconductor test apparatus for testing a semiconductor device using the timing pulse generation circuit described above.
[0021]
[Means for Solving the Problems]
  A timing pulse generating circuit according to claim 1 of the present invention comprises a plurality of timing generating means for generating timing pulses at a time according to a user setting,
  Waveform forming means for changing pin output each time a timing pulse is emitted from the plurality of timing generating means;
  All timing generators are in an interleaved off state in which the timing pulse can be generated within the same period, and some timing generatorsIn an active state capable of generating timing pulses within the same period, andThe remaining timing generation meansThe timing pulse can be generated within a period following the same period.Interleaving means for realizing an interleave-on state to be an active state;
  It is characterized by providing.
[0022]
According to a second aspect of the present invention, there is provided the timing pulse generating circuit according to the second aspect of the present invention, wherein the interleaving unit generates a timing pulse while the partial timing generating unit generates a timing pulse while the interleave on state is realized. The generation means alternately generates a state in which a timing pulse is generated for each period.
[0023]
In the timing pulse generating circuit according to claim 3 of the present invention, the timing generating means includes:
A counter that generates a rough pulse when the user's set value is read and the set value and the count value match,
A vernier that reads a user's set value and generates an accurate timing pulse based on the coarse pulse;
It is characterized by providing.
[0024]
In the timing pulse generation circuit according to claim 4 of the present invention, the interleaving means includes:
Interleave signal generating means for generating an interleave off signal and an interleave on signal;
When the interleave-off signal is issued, all timing generating means are activated, and when the interleave-on signal is issued, the change signal that is inverted every period is at the first level. A logic circuit that activates only some of the timing generation means under a certain condition and activates only the remaining timing generation means under a situation where the change signal is at a second level;
It is characterized by providing.
[0025]
In the timing pulse generating circuit according to claim 5 of the present invention, when the interleave-off signal is generated, the logic circuit always supplies an active signal to the enable terminals of all timing pulse generating means. When the interleave on signal is generated, one of the change signal and its inverted signal is supplied to the enable terminal of the part of the timing pulse generating means, and the enable terminal of the remaining timing pulse generating means is supplied. The other of the change signal and its inverted signal is supplied.
[0026]
A timing pulse generation circuit according to a sixth aspect of the present invention includes:
One of the counter and vernier included in the part of the timing generation means includes a first bank and a second bank that execute processing for generating a timing pulse alternately every period,
While the interleave means is realizing the interleave-on state, the timing generation means generates the timing pulse by a built-in counter and vernier, while the remaining timing generation means The timing pulse is generated using one of the first and second banks built in some timing generation means and one of the counter and vernier built in the remaining timing generation means It is.
[0027]
The timing pulse generating circuit according to claim 7 of the present invention is characterized in that the first bank and the second bank are a first counter bank and a second counter bank that generate a coarse pulse every period. It is.
[0028]
In the timing pulse generation circuit according to claim 8 of the present invention, the interleaving means includes:
Interleave signal generating means for generating an interleave off signal and an interleave on signal;
When the interleave-off signal is generated, the outputs of the first and second counter banks included in the part of the timing generation means are supplied to verniers included in the timing generation means, and the remaining timing generation occurs. When the interleave on signal is generated, the interleave off signal is supplied to the vernier provided in the timing generating means. Further, when the interleave on signal is issued, the part of the timing generating means includes Selection means for supplying an output of one counter bank to a vernier included in the timing generation means and supplying an output of the second counter bank to a vernier included in the remaining timing generation means;
It is characterized by providing.
[0029]
  The timing pulse generation circuit according to claim 9 of the present invention is characterized in that the plurality of timing generation means read the setting of the user for each cycle of generating the timing pulse.
  Claims of the invention10The semiconductor test apparatus according to claim 1 to claim 1.9A timing pulse generator circuit according to any one of
  Test processing execution means for executing processing necessary for testing on a plurality of types of semiconductor devices;
  It is characterized by providing.
[0030]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings. In addition, the same code | symbol is attached | subjected to the element which is common in each figure, and the overlapping description is abbreviate | omitted.
[0031]
Embodiment 1 FIG.
FIG. 1 is a circuit diagram of a timing pulse generation circuit according to the first embodiment of the present invention. The timing pulse generation circuit of this embodiment is a part of a semiconductor test apparatus that performs a predetermined test using an LSI such as a microcomputer, a synchronous or asynchronous memory, etc. as a device under measurement.
[0032]
As shown in FIG. 1, the timing pulse generation circuit includes a reference signal generation unit 3. The reference signal generation unit 3 outputs a reference signal that is inverted at a predetermined period and a change signal that is inverted every period that is one cycle of a processing cycle in a test that is performed by the semiconductor test apparatus.
[0033]
  The reference signal generated by the reference signal generation unit 3 is supplied to the first to nth timing generation circuits, that is, the first to nth TGs (n is an even number). The first to nth TGs include first to nth counters 1 and first to nth verniers 2, respectively. Also, enable circuits 5 are provided for the first to nth TGs, respectively. The enable circuit 5 realizes an active state by an “L” input, that is, a state in which an input signal to the TG is validated, and “H"This circuit realizes an inactive state by input, that is, a state in which an input signal to TG is invalidated.
[0034]
The first to n-th counters 1 receive the reference signal and increment the count value when the corresponding enable circuit 5 realizes the active state, and reset the count value every cycle. Each of the first to n-th counters 1 reads a user setting for each cycle of processing executed by the semiconductor test apparatus, and generates a timing pulse when the count value becomes a value corresponding to the setting. To do. According to the 1st thru | or the nth counter 1, the rough timing pulse according to a user's setting can each be produced | generated by performing said process.
[0035]
  The first to n-th vernier 2 is supplied with output pulses of the first to n-th counter 1, respectively, and via a delay circuit,StandardA reference signal, that is, a delayed reference signal is supplied from the signal generator 3. The first to n-th vernier 2 takes OR logic of the output pulses of the first to n-th counters 1 and the delayed reference signal, and generates a desired timing pulse based on the resulting signal. Each of the first to n-th verniers 2 reads a user's setting every cycle and generates a timing pulse so that an edge that exactly matches the setting is obtained. According to the 1st thru | or the nth vernier 2, by performing said process, each can generate the timing pulse corresponding to a user's setting correctly.
[0036]
  The timing pulse generation circuit of the present embodiment includes a plurality of functional units 6. One function unit 6 is provided for two adjacent TGs. The function unit 6Odd numberA two-input NOR circuit 604 connected to the enable circuit 5 corresponding to the th TG, andEven numberA two-input NOR circuit 605 connected to the enable circuit 5 corresponding to the TG is provided.
[0037]
A change signal is supplied from the reference signal generator 3 to one input terminal of the NOR circuit 604. A change signal is supplied from the reference signal generator 3 to one input terminal of the NOR circuit 605 via the inverter circuit 606. Further, the output signal of the D flip-flop 603 is supplied to the other input terminal of these two NOR circuits.
[0038]
The D flip-flop 603 is controlled by a bus signal supplied from the CPU of the semiconductor test apparatus or a high-speed signal supplied via a dedicated line. Specifically, the D flip-flop 603 generates an “H” output or an “L” output in response to these bus signals or high-speed signals.
[0039]
  The functional unit 6 includes a 2-input AND circuit 601. One input terminal of the AND circuit 601 hasOdd numberThe output signal of vernier 2 included in the th TG is supplied. Further, the output signal of the 2-input OR circuit 607 is supplied to the other input terminal of the AND circuit 601. The input terminal of the OR circuit 607 hasEven numberThe vernier output signal included in the second TG and the output signal of the D flip-flop 603 are supplied.
[0040]
  The function unit 6 further includes a 2-input NAND circuit 602. One input terminal of the NAND circuit 602 is connected via an inverter circuit 608.Even numberThe output signal of vernier 2 included in the th TG is supplied. Further, the output signal of the D flip-flop 603 is supplied to the other input terminal of the NAND circuit 602. Both the output signal of the AND circuit 601 and the output signal of the NAND circuit 602 are supplied to the waveform forming circuit 4.
[0041]
The waveform forming circuit 4 is provided corresponding to one output pin. The waveform forming circuit 4 is a circuit that inverts the pin output every time a timing pulse is supplied from either the AND circuit 601 or the NAND circuit 602.
[0042]
The timing pulse output from the waveform forming circuit 4 is supplied to one pin of the device under measurement or to a determination circuit built in the semiconductor test apparatus. When the timing pulse is supplied to pin 1 of the device under measurement, for example, it is used as an address signal or a clock signal. On the other hand, when the timing pulse is supplied to the determination circuit, it is used as a signal for determining the timing for determining the output of the device under measurement.
[0043]
Next, the operation of the timing pulse generation circuit of this embodiment will be described with reference to FIGS.
FIG. 2 shows a state where the D flip-flop 603 generates an “H” output. When the D flip-flop 603 generates the “H” output, the input of the enable circuit 5 is fixed to the “L” input. Accordingly, in this case, the first to nth TGs are always in the active state.
[0044]
  When the D flip-flop 603 generates an “H” output, the input to one input terminal of the AND circuit 601 is fixed to the “H” input, and the input to one input terminal of the NAND circuit 602 is “H"In this case, the timing pulse emitted from the odd-numbered TG is supplied to the waveform forming circuit 4 via the AND circuit 601 and the timing pulse emitted from the even-numbered TG passes through the NAND circuit 602. Via the waveform forming circuit 4.
[0045]
That is, when the D flip-flop 603 generates an “H” output, each of the first to n-th TGs generates a timing pulse toward the waveform forming circuit 4 at an appropriate time corresponding to a user setting. . In this case, the first to n-th TGs can supply a maximum of n timing pulses to the waveform forming circuit 4 within one cycle of processing executed by the semiconductor test apparatus.
[0046]
FIG. 3 shows an example of a timing chart realized in the above situation, that is, in a situation where the D flip-flop 603 emits an “H” output.
Under the above situation, as shown in FIGS. 3C and 3D, the first and second TGs are always maintained in the on state, that is, the active state.
[0047]
FIGS. 3E and 3F show the set values of the first and second TGs, that is, the times when these TGs are set by the user as the times when the timing pulses should be generated. When the first and second TGs are always in the active state, the timing pulses generated from these TGs are, after a predetermined delay, an AND circuit 601 and a NAND circuit, as shown in FIGS. 3 (G) and (H). 602 is output. Therefore, in this case, as shown in FIG. 3I, it is possible to obtain a pin output that inverts the output every time each TG generates a timing pulse within the same period.
[0048]
Next, the influence of the timing dead zone in the timing pulse generation circuit of this embodiment will be described with reference to FIG.
FIG. 4 shows that the output signal of the D flip-flop 603 is an “H” signal, and the first TG generates a timing pulse at the end of the cycle 1 as shown in FIG. The timing chart implement | achieved in the condition set to is shown.
[0049]
  As described above, the first TG reads a user setting every cycle and generates a timing pulse at a timing according to the setting. For this reason, after generating the timing pulse, the processing of the timing data is completed.UntilDuring this predetermined period, a new timing pulse cannot be generated. For the above reasons,When the timing pulse generation timing of the first TG in the cycle 1 is set just before the end of the cycle 1 as shown in FIG. 4 (E), after the cycle 2 is started, the predetermined period is a timing dead zone. It becomes.
[0050]
When the timing pulse generation circuit is required to generate a timing pulse at a high speed, a situation occurs in which the first TG is required to generate a timing pulse within the timing dead zone. obtain. In this case, if the output of the D flip-flop 603 is fixed to the “H” output, a desired timing pulse cannot be generated as shown in FIG. 4G, and as a result, as shown in FIG. As a result, the pin output cannot be reversed at a desired timing.
[0051]
FIG. 5 shows a state in which the output of the D flip-flop 603 is fixed to the “L” output in the timing pulse generation circuit of this embodiment. When the output of the D flip-flop 603 is an “L” output, the input of the enable circuit 5 depends on the change signal generated by the reference signal generator 3. Accordingly, in this case, the odd-numbered TG group and the even-numbered TG group are alternately activated in every cycle.
[0052]
When the output of the D flip-flop 603 is an “L” output, the AND circuit 601 receives the output signal of the even-numbered TG through the OR circuit 607 of the preceding stage together with the output signal of the odd-numbered TG. Supplied. Accordingly, in this case, the AND circuit 601 alternately supplies the odd-numbered TG output and the even-numbered TG output to the waveform forming circuit 4 every cycle. On the other hand, when the output signal of the D flip-flop 603 is fixed to the “L” output, the output of the NAND circuit 602 is fixed to the “H” output. Therefore, in this case, the timing pulse is not supplied from the NAND circuit 602 to the waveform forming circuit 4.
[0053]
FIG. 6 shows a timing chart realized under the above situation, that is, under the situation where the output of the D flip-flop 603 is fixed to the “L” output.
In the timing chart shown in FIG. 6, as shown in FIGS. 6E and 6F, the timing pulse generation timing of the first TG is set just before the end of the period 1, and the timing pulse generation of the second TG is generated. This is realized when the time is set just before the end of the cycle 2.
[0054]
When the output of the D flip-flop 603 is fixed to the “L” output, the timing pulse is emitted from the first TG in the period 1, while the timing pulse is not emitted from the second TG. For this reason, as shown in FIG. 6F, the second TG can appropriately generate a timing pulse immediately after the period 2 is started.
[0055]
When the output of the D flip-flop 603 is fixed to the “L” output, the timing pulse emitted from the first TG and the timing pulse emitted from the second TG are shown in FIG. As described above, both are output from the AND circuit 601. As a result, two timing pulses are generated at a timing without a timing dead zone. Therefore, under the above situation, as shown in FIG. 6I, a desired pin tip waveform can be formed without being affected by the timing dead zone.
[0056]
As described above, according to the timing pulse generation circuit of the present embodiment, when it is necessary to generate a timing pulse within one cycle using all of a plurality of TGs corresponding to the same pin, the interleaving function is turned off. Thus, it is possible to realize a state in which all the TGs generate timing pulses at appropriate timings set individually within the same period. Also, when there is a TG that does not need to be used among a plurality of TGs corresponding to the same pin, the interleave function can be turned on to enable timing setting without a timing dead zone.
[0057]
When the device under measurement is, for example, a high-speed microcomputer or a high-speed synchronous memory, only one timing pulse may be set in one period for the execution of the test. On the other hand, when the device under test is, for example, an asynchronous memory, it is necessary to set a plurality of timing pulses within one cycle in order to execute the test.
[0058]
According to the timing pulse generation circuit of the present embodiment, the number of timing pulses generated within one period can be changed, and when an unused TG occurs, a timing dead zone is generated using the TG. Can be prevented. For this reason, according to the timing pulse generation circuit of this embodiment, various situations required for testing various devices under measurement can be efficiently realized.
[0059]
In the present embodiment, the timing pulse generation circuit is mounted on a semiconductor test apparatus having a function of executing a plurality of tests for various devices under measurement. More specifically, it is mounted and used in a semiconductor test apparatus having a function for executing a plurality of tests for a high-speed microcomputer, a high-speed synchronous memory, an asynchronous memory, and the like. According to the semiconductor test apparatus of this embodiment, in addition to the above-described various LSIs, for example, tests relating to various LSIs such as a microcomputer with built-in memory and a memory-embedded ASIC can be efficiently executed.
[0060]
In the above embodiment, the first to nth TGs are included in the “timing generator” according to the first aspect, and the waveform forming circuit 4 is included in the “waveform generator” according to the first aspect. 6 corresponds to the “interleaving means” described in claim 1.
[0061]
In the above embodiment, one of the odd-numbered and even-numbered TGs is “part of timing generating means” according to claim 2, and the other is “remaining timing generating means” according to claim 2. Respectively.
[0062]
In the above embodiment, the first to nth counters correspond to the “counter” according to the third aspect, and the first to nth verniers correspond to the “vernier” according to the third aspect. .
[0063]
In the above embodiment, the D flip-flop 603 is the “interleave signal generating means” according to the fourth aspect, and the NOR circuits 604 and 605 and the inverter circuit 606 are the “logic circuit” according to the fourth or fifth aspect. Respectively.
[0064]
Embodiment 2. FIG.
Next, a second embodiment of the present invention will be described with reference to FIGS. FIG. 7 shows a circuit diagram of a timing pulse generation circuit according to the second embodiment of the present invention. Similar to the timing pulse generation circuit of the first embodiment, the timing pulse generation circuit of the present embodiment is a semiconductor test apparatus that performs a predetermined test using an LSI such as a microcomputer or a synchronous or asynchronous memory as a device to be measured. Is part of. In FIG. 7, the same components as those shown in FIG. 1 are designated by the same reference numerals, and the description thereof is omitted.
[0065]
  As shown in FIG. 7, in the timing pulse generation circuit of this embodiment, the first to nth TGs include first to nth counters 7, respectively. In the present embodiment, the reference signal generator 3 generates a load signal together with the above-described reference signal and change signal. The load signal is a signal composed of pulse signals of a predetermined interval that are repeatedly issued every test period. These signals areStandardThe signal is supplied from the signal generator 3 to the first to n-th counters 7.
[0066]
FIG. 8 shows a circuit diagram of the first counter 7. The first to nth counters 7 are the same in configuration. For this reason, the structure of the 1st counter 7 is demonstrated as those typical examples here.
The first counter 7 includes a first counter bank 701 for odd test cycles and a second counter bank 702 for even test cycles. The output signal of the OR circuit 711 is supplied to the load terminal LD of the first counter bank 701. The OR circuit 711 is supplied with a load signal and an inverted signal of the change signal.
[0067]
On the other hand, the output signal of the OR circuit 712 is supplied to the load terminal LD of the second counter bank 702. The OR circuit 712 is supplied with a load signal and a change signal. According to the above structure, the load signals supplied to the first and second counter banks 701 and 702 are made invalid signals for each cycle by the change signal. The first and second counter banks 701 and 702 are counters that increment the count value using the reference signal as an input signal and clear the count value when a pulse signal (edge) is input to the LD terminal. Accordingly, each of the first and second counter banks 701 and 702 performs count value increment processing with two test periods as one unit.
[0068]
The first counter 7 includes a memory 703. The memory 703 is a memory that stores user settings regarding test execution conditions. The memory 703 outputs the stored setting data D0 (15, 0) every cycle. Data D0 (15, 0) output from the memory 703 is supplied to the latch circuits 704 and 705. The latch circuits 704 and 705 receive the data D0 (15, 0) in response to the up edge of the output signal or inverted output signal of the toggle circuit 708, respectively.
[0069]
The toggle circuit 708 is a circuit that inverts the output using the load signal as a clock signal. According to the above structure, the latch circuits 704 and 705 can alternately take in the data D0 (15, 0) every one test cycle, and hold the fetched data for two test cycles in each circuit. it can.
[0070]
The output data D0 from the latch circuits 704 and 705 is supplied to the comparison circuits 706 and 707, respectively. The comparison circuits 706 and 707 are supplied with output signals from the first or second counter bank 701 and 702, respectively. NAND circuits 713 and 714 are connected to the comparison circuits 706 and 707, respectively. The NAND circuits 713 and 714 maintain their outputs at “H” when the count values of the first or second counter banks 701 and 702 and the output data D0 of the latches 704 and 705 are different from each other. Thus, an output pulse is generated.
[0071]
Outputs of the NAND circuits 713 and 714 are supplied to D flip-flops 709 and 710. The D flip-flops 709 and 710 output the outputs of the NAND circuits 713 and 714 to the outside using the delay signal of the reference signal as a clock signal. Hereinafter, the outputs of the D flip-flops 709 and 710 are referred to as a first bank output and a second bank output, respectively.
[0072]
FIG. 9 is a timing chart for explaining the operation of the first counter 7. In the timing chart shown in FIG. 9, as shown in FIGS. 9J and 9K, the latch circuit 704 latches the user setting value “1” in period 1 and the latch circuit 705 in the period 2 Is a timing chart realized when the set value “2” is latched and the latch circuit 704 latches the user set value “1” in period 3.
[0073]
As shown in FIGS. 9 (O) and 9 (P), the first counter 7 alternates with the first bank when the user's set value and the count value of the first or second counter bank coincide with each other. Output and second bank output are generated. In the present embodiment, the first to n-th counters 7 are characterized in that they are provided with lines that emit alternate output signals every period as described above.
[0074]
As shown in FIG. 7, the timing pulse generation circuit of this embodiment includes a plurality of functional units 8. One functional unit 8 is provided for each of two adjacent TGs. Each functional unit 8 includes an OR circuit 804 corresponding to each of the first to n-th counters 7. The OR circuits 804 are supplied with the first and second bank outputs from the first to n-th counters 7.
[0075]
The function unit 8 includes two selection circuits 805 and 806. The selection circuits 805 and 806 include two input terminals (A terminal and B terminal), a select terminal SL, and an output terminal Q. The selection circuits 805 and 806 output a signal supplied to the A terminal when the “L” signal is supplied to the select terminal SL, and when the “H” signal is supplied to the select terminal SL. It is a circuit that outputs a signal supplied to the B terminal.
[0076]
The first bank output of the counter 7 provided in the odd-numbered TG and the output of the OR circuit 804 corresponding to the counter 7 are supplied to the A terminal and the B terminal of one selection circuit 805, respectively. The output of the selection circuit 805 is supplied to the corresponding vernier 2.
[0077]
The A terminal and the B terminal of the other selection circuit 806 receive the second bank output of the counter 7 included in the odd-numbered TG and the ORs receiving the first and second bank outputs from the even-numbered counter 7, respectively. The output of circuit 804 is supplied. The output of the selection circuit 806 is supplied to the corresponding vernier 2.
[0078]
The output signal of the D flip-flop 803 is supplied to the select terminals SL of the selection circuits 805 and 806. The D flip-flop 803 is controlled by a bus signal supplied from the CPU of the semiconductor test apparatus or by a high-speed signal supplied via a dedicated line, like the D flip-flop 603 in the first embodiment.
[0079]
The functional unit 8 includes a two-input AND circuit 801, a two-input NAND circuit 802, an OR circuit 607, and inverter circuits 807 and 808. As in the AND circuit 601, NAND circuit 602, OR circuit 607, and inverter circuit 608 in the first embodiment, these output signals of the first to nth vernier 2 are output in accordance with the output signal of the D flip-flop 803. The data is transmitted to the waveform forming circuit 4 as appropriate.
[0080]
Next, the operation of the timing pulse generation circuit of this embodiment will be described.
FIG. 10 shows a state where the output of the D flip-flop 803 is fixed at “H”. When the output of the D flip-flop 803 is fixed to “H”, an “H” output is supplied to the select terminal SL. In this case, the selection circuits 805 and 806 select the B input. As a result, the selection circuit 805 supplies the output of the OR circuit 804 corresponding to the odd-numbered TG to the vernier 2. On the other hand, the selection circuit 806 supplies the output of the OR circuit 804 corresponding to the even-numbered TG to the vernier 2.
[0081]
When the D flip-flop 803 generates an “H” output, the input to one input terminal of the AND circuit 801 is fixed to the “H” input, and the input to one input terminal of the NAND circuit 802 is Fixed to “L” input. In this case, the AND circuit 801 supplies the waveform forming circuit 4 with the output signal of the vernier 2 included in the odd-numbered TG. Further, the NAND circuit 802 supplies the waveform forming circuit 4 with the output signal of the vernier 2 included in the even-numbered TG.
[0082]
Accordingly, when the D flip-flop 803 generates an “H” output, the first to n-th TGs are directed to the waveform forming circuit 4 at an appropriate time corresponding to the user setting for each test period. Timing pulses can be supplied. In this case, the timing pulse generation circuit can generate a maximum of n timing pulses within one test cycle.
[0083]
FIG. 11 shows an example of a timing chart realized under the above situation, that is, under the situation where the D flip-flop 803 emits an “H” output.
Under the above situation, as shown in FIGS. 11 (I) and (J), the first and second vernier 2 each generate a timing pulse at an appropriate time according to the user's setting for each period.
[0084]
In the above situation, as shown in FIGS. 11K and 11L, timing pulses output from the first and second vernier 2 are output from the AND circuit 801 and the NAND circuit 802, respectively. Therefore, in this case, as shown in FIG. 11M, it is possible to obtain a pin output that inverts the output every time each TG generates a timing pulse within the same period.
[0085]
Next, the influence of the timing dead zone in the timing pulse generation circuit of this embodiment will be described with reference to FIG.
FIG. 12 shows that the output signal of the D flip-flop 803 is an “H” signal, and the first TG generates a timing pulse at the end of the period 1 as shown in FIG. The timing chart implement | achieved in the condition set to is shown.
[0086]
The first TG reads a user's setting every cycle and generates a timing pulse at a timing according to the setting. For this reason, after a timing pulse is generated, a new timing pulse cannot be generated during a predetermined period between completion of timing data processing and the like. For the above reasons, when the timing pulse generation timing of the first TG in the cycle 1 is set just before the end of the cycle 1 as shown in FIG. The period is a timing dead zone.
[0087]
When the timing pulse generation circuit is required to generate a timing pulse at a high speed, a situation occurs in which the first TG is required to generate a timing pulse within the timing dead zone. obtain. In this case, when the output of the D flip-flop 803 is fixed to the “H” output, a desired timing pulse cannot be generated as shown in FIG. 12K, and as a result, as shown in FIG. As a result, the pin output cannot be reversed at a desired timing.
[0088]
FIG. 13 shows a state in which the output of the D flip-flop 803 is fixed to the “L” output in the timing pulse generation circuit of this embodiment. When the output of the D flip-flop 803 is “L” output, the selection circuits 805 and 806 select the A input. Therefore, in this case, the first bank output and the second bank output of the counter included in the odd-numbered TG are supplied to the odd-numbered vernier 2 and the even-numbered vernier 2, respectively.
[0089]
When the output of the D flip-flop 803 is an “L” output, the output signal of the even-numbered TG is supplied to the AND circuit 801 through the OR circuit 807 of the previous stage together with the output signal of the odd-numbered TG. Is done. Therefore, in this case, the AND circuit 801 alternately supplies the odd-numbered TG output and the even-numbered TG output to the waveform forming circuit 4 every cycle. On the other hand, when the output signal of the D flip-flop 803 is fixed to the “L” output, the output of the NAND circuit 802 is fixed to the “H” output. Therefore, in this case, the timing pulse is not supplied from the NAND circuit 902 to the waveform forming circuit 4.
[0090]
FIG. 14 shows a timing chart realized under the above situation, that is, under the situation where the output of the D flip-flop 803 is fixed to the “L” output.
In the timing chart shown in FIG. 14, as shown in FIGS. 14I and 14J, the timing pulse generation timing of the first TG is set just before the end of the cycle 1, and the timing pulse generation of the second TG is generated. This is realized when the time is set just before the end of the cycle 2.
[0091]
When the output of the D flip-flop 803 is fixed to the “L” output, in the period 1, the first bank output of the first counter is emitted as a timing pulse from the first TG, while the second vernier 2 (second From (TG), no timing pulse is emitted. For this reason, as shown in FIG. 14J, the second vernier 2 can appropriately generate a timing pulse immediately after the period 2 is started.
[0092]
Further, when the output of the D flip-flop 803 is fixed to the “L” output, the timing pulse emitted from the first TG and the timing pulse emitted from the second TG are shown in FIG. As described above, both are output from the AND circuit 801. As a result, two timing pulses are generated at a timing without a timing dead zone. Therefore, under the above situation, as shown in FIG. 14I, a desired pin tip waveform can be formed without being affected by the timing dead zone.
[0093]
As described above, according to the timing pulse generation circuit of the present embodiment, when it is necessary to generate a timing pulse within one cycle using all of a plurality of TGs corresponding to the same pin, the interleaving function is turned off. Thus, it is possible to realize a state in which all the TGs generate timing pulses at appropriate timings set individually within the same period. Also, when there is a TG that does not need to be used among a plurality of TGs corresponding to the same pin, the interleave function can be turned on to enable timing setting without a timing dead zone. For this reason, according to the timing pulse generation circuit of the present embodiment, as in the case of the first embodiment, various situations required for testing various devices under measurement can be efficiently realized. .
[0094]
In particular, the timing generation circuit of the present embodiment realizes the desired function described above by interleaving only the vernier 2. By interleaving only vernier 2, the memory capacity required for interleaving can be reduced as compared with the case where both counter 1 and vernier 2 are interleaved. Therefore, according to the timing generation circuit of the present embodiment, it is possible to obtain an effect that a desired function can be realized with a smaller memory capacity than the circuit of the first embodiment.
[0095]
In the present embodiment, the timing pulse generation circuit is mounted and used in a semiconductor test apparatus having a function of executing a plurality of tests for various devices under measurement. More specifically, it is mounted and used in a semiconductor test apparatus having a function for executing a plurality of tests for a high-speed microcomputer, a high-speed synchronous memory, an asynchronous memory, and the like. According to the semiconductor test apparatus of this embodiment, in addition to the above-described various LSIs, for example, tests relating to various LSIs such as a microcomputer with built-in memory and a memory-embedded ASIC can be efficiently executed.
[0096]
In the above-described embodiment, the first counter bank 701 and the second counter bank 702 are respectively referred to as the “first bank” and the “second bank” according to the sixth aspect, and the function unit 8 is as defined in the above claim. This corresponds to “the interleaving means” described in 6.
[0097]
In the above embodiment, the D flip-flop 803 is the “interleave signal generating means” according to the eighth aspect, and the OR circuit 804 and the selection circuits 805 and 806 are the “selecting means” according to the eighth aspect. Respectively.
[0098]
【The invention's effect】
Since the present invention is configured as described above, the following effects can be obtained.
According to the first aspect of the present invention, it is possible to realize a state in which all timing generating means can individually generate timing pulses and a state in which a timing dead zone can be avoided by using timing generating means that is not used. Can do. For this reason, according to the timing pulse generation circuit of the present invention, it is possible to execute tests on various semiconductor devices.
[0099]
According to the second aspect of the present invention, a part of the timing generating means and the remaining timing generating means alternately generate timing pulses, so that the desired timing can be continuously obtained without being affected by the timing dead zone. Can be generated.
[0100]
According to the third aspect of the present invention, it is possible to generate a highly accurate timing pulse with a simple structure by generating a coarse pulse with a counter and increasing the accuracy of the coarse pulse with a vernier.
[0101]
According to the fourth aspect of the present invention, in the interleave-off state, by setting all the timing generation means to the active state, it is possible to realize a state where all of them can generate timing individually. In the interleave-on state, some timing generating means and the remaining timing generating means can be alternately activated in each cycle. In this case, since a timing pulse generation request is generated every other period for a part of the timing generation means and the remaining timing generation means, generation of a timing dead zone can be prevented.
[0102]
According to the invention described in claim 5, the function described in claim 4 can be realized with a simple structure.
[0103]
According to the sixth aspect of the present invention, in the interleaved state, it is necessary to store user settings in both the counter and the vernier for some timing generation means, but for the remaining timing generation means, the counter and A desired function can be realized by storing the user settings in only one of the verniers. Therefore, according to the present invention, a desired function can be realized with a small memory capacity.
[0104]
According to the invention described in claims 7 and 8, the function described in claim 6 can be realized with a simple structure.
[0105]
  Claim10According to the described invention, the timing generation circuit can be applied to various semiconductor devices, and the semiconductor device itself has a function of executing tests on various semiconductor devices. Therefore, according to the semiconductor test apparatus of the present invention, it is possible to efficiently perform a test using various semiconductor devices as devices under measurement.
[Brief description of the drawings]
FIG. 1 is a circuit diagram of a timing pulse generation circuit according to a first embodiment of the present invention.
FIG. 2 is a circuit diagram of the timing pulse generation circuit shown in FIG. 1 under an interleave-off state.
FIG. 3 is a timing chart for explaining the operation of the timing pulse generation circuit shown in FIG. 1 under an interleave-off state.
FIG. 4 is a timing chart for explaining the influence of a timing dead zone in the timing pulse generation circuit shown in FIG. 1;
FIG. 5 is a circuit diagram of the timing pulse generating circuit shown in FIG. 1 under an interleave on state.
6 is a timing chart for explaining the operation of the timing pulse generation circuit shown in FIG. 1 under an interleave-on state. FIG.
FIG. 7 is a circuit diagram of a timing pulse generation circuit according to a second embodiment of the present invention.
FIG. 8 is a circuit diagram of a first counter provided in the timing pulse generation circuit shown in FIG. 1;
FIG. 9 is a timing chart for explaining the operation of the first counter shown in FIG. 8;
10 is a timing chart for explaining the operation of the timing pulse generation circuit shown in FIG. 7 under an interleave-off state.
11 is a timing chart for explaining the operation of the timing pulse generation circuit shown in FIG. 7 under the interleave-off state.
12 is a timing chart for explaining the influence of a timing dead zone in the timing pulse generation circuit shown in FIG. 7; FIG.
13 is a circuit diagram of the timing pulse generation circuit shown in FIG. 7 under an interleave on state. FIG.
14 is a timing chart for explaining the operation of the timing pulse generation circuit shown in FIG. 1 under an interleave-on state. FIG.
FIG. 15 is a circuit diagram of a conventional timing pulse generation circuit.
16 is a timing chart for explaining the influence of a timing dead zone in the timing pulse generation circuit shown in FIG.
FIG. 17 is a circuit diagram of a conventional timing pulse generation circuit having an interleaving function.
[Explanation of symbols]
1; 7 1st to n-th counter, 2 1st to n-th vernier, 3 reference signal generator, 4 waveform forming circuit, 5 enable circuit, 6; 8 function unit, 603; 803 D flip-flop, 805, 806 selection Circuit, TG timing generator.

Claims (10)

  1. A plurality of timing generating means for generating a timing pulse at a time according to a user setting;
    Waveform forming means for changing pin output each time a timing pulse is emitted from the plurality of timing generating means;
    An interleave-off state in which all timing generation means are in an active state capable of generating timing pulses within the same period, and a part of the timing generation means are in an active state capable of generating timing pulses within the same period, And interleaving means for realizing an interleave on state in which the remaining timing generating means is in an active state capable of generating timing pulses within a period following the same period ,
    A timing pulse generation circuit comprising:
  2.   While the interleave on state is realized, the interleaving means is configured so that a state in which the part of timing generating means generates timing pulses and a state in which the remaining timing generating means generates timing pulses are generated every period. 2. The timing pulse generating circuit according to claim 1, wherein the timing pulse generating circuit is alternately generated.
  3. The timing generating means includes
    A counter that reads a user's set value and generates a coarse pulse when the set value and the count value match;
    A vernier that reads a user's set value and generates an accurate timing pulse based on the coarse pulse;
    The timing pulse generation circuit according to claim 2, further comprising:
  4. The interleaving means is
    Interleave signal generating means for generating an interleave off signal and an interleave on signal;
    When the interleave-off signal is issued, all timing generating means are activated, and when the interleave-on signal is issued, the change signal that is inverted every cycle is at the first level. A logic circuit that activates only some of the timing generation means under a certain condition and activates only the remaining timing generation means under a situation where the change signal is at a second level;
    The timing pulse generation circuit according to claim 1, further comprising:
  5.   When the interleave-off signal is generated, the logic circuit always supplies an active signal to the enable terminals of all timing pulse generating means, and when the interleave-on signal is generated. Supplying one of the change signal and its inverted signal to the enable terminals of the part of the timing pulse generating means, and supplying the other of the change signal and its inverted signal to the enable terminal of the remaining timing pulse generating means. The timing pulse generation circuit according to claim 4.
  6. One of the counter and vernier included in the part of the timing generation means includes a first bank and a second bank that execute processing for generating a timing pulse alternately for each period,
    The interleaving means, while the interleave on state is realized, causes the some timing generation means to generate the timing pulse by a built-in counter and vernier, while the remaining timing generation means The timing pulse is generated using one of first and second banks built in some timing generation means and one of a counter and vernier built in the remaining timing generation means. Item 4. The timing pulse generation circuit according to Item 3.
  7.   7. The timing pulse generation circuit according to claim 6, wherein the first bank and the second bank are a first counter bank and a second counter bank that generate a coarse pulse for each period.
  8. The interleaving means is
    Interleave signal generating means for generating an interleave off signal and an interleave on signal;
    When the interleave-off signal is generated, the outputs of the first and second counter banks included in the part of the timing generation means are supplied to verniers included in the timing generation means, and the remaining timing generation occurs. When the interleave on signal is generated, the interleave off signal is supplied to the vernier provided in the timing generating means. Further, when the interleave on signal is issued, the part of the timing generating means includes Selecting means for supplying an output of one counter bank to a vernier included in the timing generation means and supplying an output of the second counter bank to a vernier included in the remaining timing generation means;
    8. The timing pulse generation circuit according to claim 7, further comprising:
  9.   9. The timing pulse generation circuit according to claim 1, wherein the plurality of timing generation units read the setting of the user for each cycle of generating the timing pulse.
  10. A timing pulse generation circuit according to any one of claims 1 to 9,
    Test processing execution means for executing processing necessary for testing on a plurality of types of semiconductor devices;
    A semiconductor test apparatus comprising:
JP15568598A 1998-06-04 1998-06-04 Timing pulse generation circuit and semiconductor test apparatus Expired - Fee Related JP4215860B2 (en)

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