JPS58222534A - Integrated circuit - Google Patents

Abstract

PURPOSE:To enable a test at high speed by incorporating a circuit exclusive for a small-scale test. CONSTITUTION:When a test terminal 10 is brought to ''1'', a selecting circuit 8 selects an output from a selecting circuit 6, and selects an output from the frequency dividing circuit 5 of the selecting circuit 6. A processing mode before and after the test is obtained by a low-speed clock, and an input pattern to an internal logic ''1'' is prepared. When ''1'' is inputted to a test starting terminal 11 and a test execution FF13 is set to ''1'', the selecting circuit 6 selects a high- speed clock of an oscillation circuit 4, and a test execution mode is obtained. A counter 15 down-counts every time clocks enter, a ''1'' output is generated and the FF13 reaches ''0'' when contents reach ''0'', and the processing mode before and after the test is obtained again. The low-speed clock is generated, the contents of an output register 3 are read, and the results of the test of a logic function are acquired.

Description

[Detailed description of the invention] [Technical field of invention] The present invention relates to integrated circuits with test functionality.

[Technical background of the invention and its problems]

Recently, there has been a trend toward further miniaturization of integrated circuits.

Along with this, ultra-high speeds are being promoted.

In conventional integrated circuits, an appropriate input cover pattern is applied, pass/fail is determined based on whether the output pattern matches the correct answer pattern, and if the output pattern does not match the correct answer pattern, it is considered to be defective. Also, a so-called delay time test is conducted to test when the output cover turn is determined to be 0 or 1, that is, whether the time from the moment the input cover turn is given to the appearance of the output cover turn satisfies the specification value. .

However, as the speed of integrated circuits increases, the time from input to output becomes extremely short, so conventional IC testers cannot handle this, and for this reason a new tester for high-speed integrated circuits has been developed. It is hoped that

However, developing a new high-speed IC tester like this has the drawback of increasing the economic burden.

[Purpose of the invention]

This invention was made in view of the above circumstances.

An object of the present invention is to provide an integrated circuit having a test circuit that enables high-speed testing.

[Summary of the invention]

A test circuit is provided that has means for generating a high-speed clock for the internal logic having the circuit under test, means for generating a low-speed clock obtained by dividing the high-speed clock, and selection means for selecting either the high-speed clock or the low-speed clock. In the test pre-processing mode, select a low-speed clock using the 4 selection means, prepare an input cover turn using this low-speed clock, then wait for the test execution mode, select a multi-cycle high-speed clock using the selection means, and select the first Input the human cover turn to the circuit under test using a high-speed clock, capture the output cover turn of the circuit under test using the following high-speed clock, read this output using the low-speed clock of the test pre-processing mode, and perform test judgment. That's what I do.

〔Effect of the invention〕

Optimal test results can be obtained even for high-speed integrated circuits,
Furthermore, it is economically advantageous because only a small circuit dedicated to testing is incorporated. It also has the advantage of being able to perform tests over multiple cycles as a test execution mode.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows a case where the entire internal logic is the circuit under test.

In the figure, reference numeral 1 denotes an internal logic, and this internal logic 1 has an input register 2 and an output register 3 on the output side.

On the other hand, 4 is an oscillation circuit, and this oscillation circuit 4 includes, for example, an odd number of NOT circuits connected in series to oscillate a high-speed clock. A frequency dividing circuit 5 for dividing the frequency of the high speed clock is connected to the output terminal of this oscillation circuit 4. In this case, the frequency dividing circuit 5 divides the frequency of the high speed clock into 1/4 to generate a low speed clock.

It has two flip-flops 51 and 52.

The output terminal of the oscillation circuit 4 is connected to one input terminal of the first selection circuit 6, and the output terminal of the frequency dividing circuit 5 is connected to the other input terminal of the selection circuit 6, and an external output terminal is connected to the output terminal of the oscillation circuit 4. 7 is already connected.

The output terminal of the first selection circuit 6 is connected to one input terminal of the second selection circuit 8. This second selection circuit 8 has its other input terminal connected to an external clock terminal 9, its output terminal connected to the internal logic 1, and its selection control terminal connected to a test terminal 10.

11 is a test start terminal for instructing the test execution mode;
This terminal 11 is connected to the D terminal of a test execution flip-flop 13 via an AND circuit 2. This flip-flop 13 becomes "1" in the test execution mode and becomes "0#" at the end of the test execution mode, and its Q terminal is connected to the selection control terminal of the first selection circuit 6, and the frequency dividing circuit are connected to the CLR terminals of flip-flops 51 and 52, respectively.

CLK 4A is connected to the selection control terminal of the second selection circuit 8.

The Q terminal of the flip-flop 13 and the output terminal of the second selection circuit 8 are connected to a counter 15 via an AND circuit 14. This counter 15 is set to a predetermined value in advance, and counts down by 1 for each cycle of the clock output from the second selection circuit 8 in the test execution mode. 121 AND circuits are connected. In this case, the value set in counter 5 is (number of cycles you want to execute -
1). Also, the logic required for setting is omitted here.

Next, its effect will be explained.

Now, set all the test terminals 10 to 1" in the test mode. Then, the second selection circuit 8 will select the output of the first selection circuit 6. At this time, the test start terminal 11
is 110 M, so the test execution flip-flop 13 is "0" and this is applied to the first selection circuit 6. This causes the first selection circuit 6 to select the output of the frequency divider circuit 5, and this output is outputted via the second selection circuit 8. In this case, from the first oscillation circuit 4,
) When the high-speed clock shown in ) is output, the divide-by-1 circuit 5 divides the high-speed clock into 1/4 and generates the low-speed clock shown in FIG. The low-speed clock shown in (f) enters the test pre-processing mode and prepares input to the internal logic 1 and Nil turn.At this time, the counter 15 is set to 1 if the number of cycles to be executed in the test execution mode is, for example, 2 cycles.
Set.

In this state, as shown in Figure 2 (C), the test start terminal 1
When inputting ``1#'' to ``1'' and setting the test execution flip-flop 13 to ``@1'' as shown in FIG. This clock is output from the second selection circuit 8, thereby entering the high-speed clock test execution mode shown in FIG. Then, the input cover turn is given to the internal logic 1 through this register 2, and after a predetermined time, the output cover turn appears on the output side, and this output cover turn is taken into the output register 3 at the next high-speed clock. .

In this test execution mode, the counter 15 counts down each time a clock is input via the AND circuit 14.

When the count reaches 0, a ``1'' output shown in Fig. 2 te+ is generated, which causes the test execution flip-flop 13 to become 0'' after waiting for the next clock. It becomes pre- and post-processing mode. Then.

A low-speed clock is generated again, and the contents of the output register 3 are read out using this low-speed clock. Therefore, when a test result of a logic function is obtained from the contents of this output register 3 to determine whether an accurate output pattern has been obtained for an input pattern, the time between the two high-speed clocks is A delay time test result is obtained to determine whether one cover turn has appeared within a predetermined allowable delay time.

Thereafter, the above-mentioned test execution mode will be obtained each time @IIT is inputted to the test start terminal 11 in the same manner.

After that, when the gold test is finished, test terminal 10
When set to 0'', the second selection circuit 8 directly selects the input from the external clock terminal 9, and henceforth enters the normal mode.

Here, the AC characteristics can be tested by measuring the output of the external output terminal 7, that is, the low-speed clock of the frequency dividing circuit 5. At this time, the AC characteristics can be tested independently of the test mode and normal mode.

Therefore, according to such a configuration, a high-speed clock is obtained for the test execution mode as well as a low-speed clock for the test pre-processing mode for the internal logic having the circuit under test, so the high-speed clock is used as the clock for measuring the delay time. By using this method, it is possible to accurately determine delay times, and optimal test results can be expected for high-speed integrated circuits. In addition, since the low-speed clock is obtained by dividing the high-speed clock, it is possible to obtain an accurate lock corresponding to the high-speed clock, thereby ensuring the preparation of the input pattern and the reading of the output pattern in the test pre-processing mode. You can also do it. Moreover, since the low-speed clock can be self-supplied within the test circuit in this way, there is an advantage that an external low-speed clock generation source can be made unnecessary.

Furthermore, since high-speed integrated circuits can be tested simply by incorporating a small-scale test-dedicated circuit, it is extremely economically advantageous compared to developing a new high-speed tester. Furthermore, in the test execution mode, a high-speed clock of multiple cycles can be obtained, so that a test can be performed over multiple cycles. Also.

Since the low-speed clock of the frequency dividing circuit is output to the outside, the AC characteristics can also be tested from this output. In this case, by using the output of the selection circuit of cylinder 1, the AC characteristics can be tested not only with a low-speed clock but also with a high-speed clock.

It should be noted that the present invention is not limited to the above-mentioned embodiments, but can be implemented with appropriate modifications without changing the gist.

For example, in the above description, the case where the high-speed clock is 2 cycles is described, but the internal logic has 9 flip-flops. If the output cover turn cannot be determined immediately for the input cover turn, including loops, and requires several clocks, a high-speed clock of several cycles may be applied. In this case, the high speed clock is also provided to the internal logic.

Further, the above-described embodiment can be applied to a case where a circuit under test including the entire internal logic is tested.

[Brief explanation of drawings]

FIG. 1 is a schematic configuration diagram showing one embodiment of the present invention, and FIG.
The figure is a time chart for explaining the same embodiment. 1...Internal logic 2...Input register 3...
・Output register 4...Oscillation circuit 5...Divider circuit 6, 8...Selection circuit 7...External output terminal
9... Clock terminal 10... Test terminal 11.
...Test start terminals 12, 14...AND circuit 13
...Test execution flip-flop 15.
...Counter 16...Knot circuit

Claims (4)

[Claims] (1) An internal logic having a circuit under test, means for generating a high-speed clock, and means for dividing the frequency of the high-speed clock to generate a low-speed clock (!:, select either the high-speed clock or the low-speed clock) selection means, the selection means selects a low-speed clock as a test pre-processing mode, and the selection means selects a high-speed clock as a test execution mode, thereby making it possible to perform various tests on the circuit under test. integrated circuit. (2) The internal logic has an input register and an output register, and the input pattern prepared by the low-speed clock in the test pre-processing mode is input to the input register at the first high-speed clock in the test execution mode. The output pattern of the internal logic is taken into an output register at a subsequent high-speed clock, and the contents of the output register are read at a subsequent low-speed clock in a test pre-processing mode. The integrated circuit according to item 1. (3) The integrated circuit according to claim 1 or 2, wherein the means for generating the high-speed clock is an odd number of not circuits connected in series. (4) The integrated circuit according to any one of claims 1 to 3, characterized in that the output of the selection means can be outputted to the outside.