JPH0682533A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To obtain a semiconductor integrated circuit requiring only one collective pin dedicated for test. CONSTITUTION:A test start signal 101 is inputted through a buffer 2 in a bi- directional buffer 1 to the clock terminal of a flip-flop 4. Output from the flip- flop 4 is inputted, as a test start signal 102 of '1' level, to a self-running self test circuit 6 and to a delay circuit 5. In the delay circuit 5, output from the flip-flop 4 is inputted, as a control signal 104, to the control terminal of a tri- state buffer 3 in the bi-directional buffer 1 while being subjected to a predetermined time lag corresponding to the time required for test thus controlling I/O state of the tri-state buffer 3. On the other hand, the test is performed automatically for a special function block 7 in the self-running self test circuit 6 which delivers a test result signal to the tri-state buffer 3 in the bi-directional buffer 1.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit,
In particular, it relates to a semiconductor integrated circuit including a self-test circuit inside.

[0002]

2. Description of the Related Art Generally, in a semiconductor integrated circuit, it is necessary to provide a test circuit in a chip of the semiconductor integrated circuit in order to efficiently test the logic function of the internal circuit. Although various methods have been considered as conventional test methods used in semiconductor integrated circuits, methods for testing special function blocks including a memory and a CPU in a semiconductor chip are roughly classified into circuit divisions. Method and self-test circuit integration method are used.

In the self-test circuit embedding method described above, as shown in the conceptual diagram of the layout of the semiconductor integrated circuit of FIG. 3, the prediction data generator 12 and the timing generator 13 are associated with the special function block 16. , A self-test circuit 11 including a data generator 14 and a data comparator 15 is built in the chip 9, and a test of the special function block 16 is executed by a signal generated in the self-test circuit 11 and the test result is obtained. Is a method of determining the quality of the special function block 16. Specifically, the timing generator 13 is started by a predetermined test start signal, whereby the test of the special function block 16 is started, and the test data for the special function block 16 to be tested is sent to the data generator 14. It is generated and input to the special function block 16. The data indicating the test result output from the special function block 16 in response to the input of the test data is compared and collated in the data comparator 14 with the prediction data of the prediction data generator 12 which generates the prediction data of the test. , The special function block 16
The quality of is automatically determined. This self-test circuit incorporation method is disclosed in, for example, Japanese Patent Application Laid-Open No. 1-161748.

[0004]

In the semiconductor integrated circuit according to the conventional self-test circuit embedding method described above, for example, when n special function blocks are built in the semiconductor integrated circuit, (n + 1) Individual test terminals are required. However, as the scale of the semiconductor integrated circuit increases, the number of terminals of the semiconductor integrated circuit itself tends to increase, and the number of package pins of the semiconductor integrated circuit is limited. There is a drawback that it becomes impossible to provide the required number of test pins.

[0005]

A semiconductor integrated circuit according to a first aspect of the present invention is a semiconductor integrated circuit including a special function block requiring a self test, and including a self test circuit for testing the special function block. , One test terminal that functions as an input of the test start signal 101 and an output of the test result signal 105 at the time of testing the special function block, and a buffer for input of the test start signal 101 corresponding to the test terminal Also, the level of the signal output from the bidirectional buffer is set to a predetermined level in response to the input of the test start signal 101 and the bidirectional buffer that functions as the buffer for outputting the test result signal 103, and the test start signal 102 is set. Receiving the test start signal 102, the special function block A self-test circuit that outputs a self-test result to the test result signal 103, and a delay that adds a predetermined time delay to the test start signal 102 and outputs the control signal 104 to the bidirectional buffer. And a circuit for controlling the input / output timing of the test start signal 101 and the test result signal 105 in the bidirectional buffer corresponding to the test terminal via the control signal 104.

The semiconductor integrated circuit of the second invention includes n special function blocks requiring self-test,
In a semiconductor integrated circuit including n self-test circuits, each of which is a test target of the special function block, a test start signal 10 is generated when the special function block is tested.
One test terminal that functions as one input and one output of the test result signal 105, and, corresponding to the test terminal, acts as an input buffer for the test start signal 101 and an output buffer for the test result signal 103. A bidirectional buffer, a level setting circuit that sets the level of the signal output from the bidirectional buffer to a predetermined level in response to the input of the test start signal 101, and outputs the test start signal 102, and the test start signal In step 102, the self-tests for the n special function blocks are individually performed, and the self-test results are respectively output as test result signals 103-1, 103-2 ,.
N-self test circuits output as 03-n and the test result signals 103-1, 103-2, ..., 103
A logical sum circuit for outputting the logical sum of −n and a predetermined time delay to the test start signal 102, and a control signal 104
As a test start signal 101 and a test result signal 105 in the bidirectional buffer corresponding to the test terminal.
It is characterized in that the timing of input / output with and is controlled via the control signal 104.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of the present invention. As shown in FIG. 1, in this embodiment, a bidirectional buffer 1 including buffers 2 and 3, a flip-flop 4, a delay circuit 5, and a free-running self-test circuit 6 are provided.
And a special function block 7.

In FIG. 1, a test start signal 101 input through a test terminal 51 is a "1" level pulse having a time width shorter than a test time required for the special function block 7 by the self-propelled self-test circuit 6. It is formed as a signal and is input to the clock terminal of the flip-flop 4 via the buffer 2 included in the bidirectional buffer 1. The output of the flip-flop 4 is the self-running self-test circuit 6 as a "1" level test start signal 102.
Is also input to the delay circuit 5. In the delay circuit 5, the input test start signal 102 undergoes a time delay of a fixed time corresponding to the test required time, and the control signal 104 is applied to the control terminal of the tri-state buffer 3 included in the bidirectional buffer 1. Is input, and acts so as to control the input / output state of the tri-state buffer 3. On the other hand, in the self-propelled self-test circuit 6, the test for the special function block 7 is automatically performed through the same test method as in the above-mentioned conventional example. The test result of this special function block 7 is output as a test result signal 103 from the self-propelled self-test circuit 6 and input to the tristate buffer 3 included in the bidirectional buffer 1. The tri-state buffer 3 changes to a state of outputting an input signal via the control signal 104 input from the delay circuit 5, and the test result signal 103 outputs the test result via the tri-state buffer 3. The signal 105 is output to the test terminal 51.

That is, the bidirectional buffer 1 is set as an input buffer because the control signal for the tri-state buffer 3 is initially input as a "0" level and its output side is set to a high impedance state. Has been done. Then, as described above, the test terminal 51
When the test start signal 101 is input from the outside via the buffer 2, it is input to the self-propelled self-test circuit 6 via the buffer 2 and the flip-flop 4, and the self-propelled self-test circuit 6 tests the special function block 7. Then, the test result is input to the tri-state buffer 3 as the test result signal 103. For this tri-state buffer 3, at this point in time, the time-delayed control signal 104 output from the delay circuit 5 is output.
Is input at the "1" level, and the bidirectional buffer 1
Is configured as an output buffer and the test result signal 10
3 is output to the test terminal 51 as the test result signal 105. Therefore, the test terminal 51 is shared as an input / output as a test terminal.

Next, a second embodiment of the present invention will be described. FIG. 2 is a block diagram showing a second embodiment of the present invention. As shown in FIG. 2, this embodiment uses the buffer 2
And bi-directional buffer 1 including tri-state buffer 3, flip-flop 4, delay circuit 5, and n self-running self-test circuits 6-1, 6-2, ..., 6-n
And n special function blocks 7-1, 7-2, ..., 7
-N and an OR circuit 8 are provided. That is, the self-propelled self-test circuits 6-1, 6-2 for testing the special function blocks 7-1, 7-2, ..., 7-n corresponding to the n special function blocks 7-1, 7-2, ..., 6-n is provided.

In this embodiment, the test start signal 101 input from the test terminal 51 is input to the flip-flop 4 via the buffer 3 and the "1" level test start signal 102 is output. It is input to the self-propelled self-test circuits 6-1, 6-2, ..., 6-n.
By these self-propelled self-test circuits, n special function blocks 7-1, 7-2, ...
, 7-n are tested, and the test result signals 103-1 of the special function blocks output from n self-propelled self-test circuits 6-1, 6-2 ,. ,
103-2, ..., 103-n are OR circuits 8 respectively.
Is input to the buffer 2, the logical sum is obtained, the test result signals are aggregated and input to the buffer 2. In this case, if there is a failure in the special function block, the test result signal of "1" level is output and input to the OR circuit 8. This OR output is the tristate buffer 3
Is output to the test terminal 51 via. Therefore, when the OR output output from the OR circuit 8 is at "1" level, the special function blocks 7-1, 7-2, ..., 7-n
It is determined that a failure has occurred. The operations of the delay circuit 5 and the tri-state buffer are the same as in the first embodiment, and the test terminal 51 is
The test result signal 105 is output. Also in this embodiment, the presence / absence of a failure can be determined by one test terminal corresponding to a plurality of special function blocks.

[0013]

As described above, the present invention is provided with a bidirectional buffer for inputting a test start signal and for outputting a test result signal, which corresponds to the input of the test start signal and the output of the test result signal. By controlling the input / output direction of the bidirectional buffer, it is possible to test the internal circuit by using only one terminal as the test terminal, which is effective in limiting the number of terminals in the semiconductor chip. It has the effect of being able to respond.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a block diagram showing a second embodiment of the present invention.

FIG. 3 is a diagram showing an outline of a layout of a conventional example.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Bidirectional buffer 2 Buffer 3 Tristate buffer 4 Flip-flop 5 Delay circuit 6, 6-1 to 6-n Self-propelled self-test circuit 7, 7-1 to 7-n, 16 Special function block 8 OR circuit 9 Chip 10 Random logic part 11 Self-test circuit 12 Prediction data generator 13 Timing generator 14 Data generator 15 Data comparator 17 Input buffer 18 Output buffer

Claims (2)

[Claims] 1. A semiconductor integrated circuit including a special function block requiring a self-test, and including a self-test circuit for testing the special function block, comprising: a test start signal 1 when the special function block is tested.
One test terminal that functions as an input of 01 and an output of the test result signal 105, and acts as an input buffer of the test start signal 101 and an output buffer of the test result signal 103 corresponding to the test terminal. A bidirectional buffer, a level setting circuit that sets the level of the signal output from the bidirectional buffer to a predetermined level in response to the input of the test start signal 101, and outputs the test start signal 102, and the test start signal In response to 102, a self-test is performed on the special function block and a self-test circuit that outputs the self-test result as a test result signal 103; and a predetermined time delay is given to the test start signal 102,
A delay circuit for outputting to the bidirectional buffer as a control signal 104; and a control signal 104 for inputting / outputting the test start signal 101 and the test result signal 105 in the bidirectional buffer corresponding to the test terminal.
A semiconductor integrated circuit characterized by being controlled via 2. A semiconductor integrated circuit including n (positive integer) special function blocks requiring a self-test, and including n self-test circuits for testing the special function blocks, wherein Test start signal 1 when testing a functional block
One test terminal that functions as an input of 01 and an output of the test result signal 105, and acts as an input buffer of the test start signal 101 and an output buffer of the test result signal 103 corresponding to the test terminal. A bidirectional buffer, a level setting circuit that sets the level of the signal output from the bidirectional buffer to a predetermined level in response to the input of the test start signal 101, and outputs the test start signal 102, and the test start signal In step 102, the self-tests on the n special function blocks are individually performed, and the self-test results are respectively output as test result signals 10
3-1, 103-2, ..., 103-n, and n self-test circuits, and the test result signals 103-1, 103-2 ,.
A logical sum circuit for outputting a logical sum of 03-n, and applying a predetermined time delay to the test start signal 102,
A delay circuit for outputting to the bidirectional buffer as a control signal 104; and a control signal 104 for inputting / outputting the test start signal 101 and the test result signal 105 in the bidirectional buffer corresponding to the test terminal.
A semiconductor integrated circuit characterized by being controlled via