JP2619957B2 - Clock control circuit for delay test - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Overview] Regarding a clock control circuit for controlling a clock for performing a delay test, an OS latch for controlling application / inhibition of a clock is provided in a latch constituting an LSI, and scan-in is performed on the OS latch. The purpose of this LSI is to suppress the application of clocks to latches other than the source latch and target latch, prevent destruction of activation conditions during delay tests, and enable delay tests with high accuracy and high diagnostic rates. The latches that hold the data to be configured are classified into a plurality of types, and OS latches for controlling the application / suppression of the clocks are provided for the classified latches. The OSs corresponding to the source latch and the target latch for which the delay test is to be performed. Scan in and set the latch to a valid value, apply a clock to the source latch and output Propagate, the clock after a predetermined time has elapsed is applied to the target latching the state uptake, configured to perform delay test.

[Industrial applications]

The present invention relates to a clock control circuit that controls a clock for performing a delay test.

[Problems to be solved by conventional technology and invention]

Conventionally, an LSI delay test has been performed as follows.

(1) A path from an external input or a latch serving as a starting point of a state change (hereinafter referred to as a source latch) to a destination latch (hereinafter referred to as a target latch) or an external output so that an internal state value is propagated so that a state change propagates. Set (activation of state propagation path).

(2) A clock is applied in a state where an input opposite to the current state of the source latch is set in the source latch, and a clock is applied to the target latch after a lapse of time required for a state change to propagate to the target latch. If there is a delay defect of an element on the propagation path, the old input state is taken into the target latch, so that the existence of the delay defect is determined.

The LSI delay test is performed according to the above procedure. Here, there is a problem that, as shown in FIG. 1, for example, the activation condition of the propagation path is destroyed in response to the application of the clock to the source latch. In order to prevent the activation condition of the propagation path from being destroyed, it is desirable to apply a clock only to the source latch. However, the conventional general logic circuit structure has a problem that it is difficult to realize this for a large number of propagation paths.

The present invention provides a method of supplying a clock to a latch constituting an LSI.
An OS latch for controlling the suppression is provided.Scanning into these OS latches suppresses the application of the clock to the latches other than the source latch and the target latch. The purpose is to enable a delay test with a high diagnostic rate.

[Means to solve the problem]

 FIG. 1 shows a principle block diagram of the present invention.

In FIG. 1, a latch 1 is a latch for holding data constituting an LSI.

The OS latch 2 is a latch that scans in data for controlling the application / inhibition of the clock to the latch 1 and sets the data.

[Action]

According to the present invention, as shown in FIG. 1, latches 1 constituting an LSI are classified into a plurality of types, and OS latches 2 for controlling application / suppression of a clock are provided for each of the classified latches 1 to perform a delay test. Source Latch 1-1
Then, the OS latch 2 corresponding to the target latch 1-2 is scanned in and set to a valid value, a clock is applied to the source latch 1-1 and its output is propagated. The state is applied to the latches 1-2 to capture the state, and a delay test is performed.

Therefore, scan into OS latch 2 and source latch
The delay test is performed in a state where the clock application to the latches 1 other than the 1-1 and target latches 1-2 is suppressed, thereby preventing the activation condition from being destroyed at the time of the delay test and achieving a high accuracy and a high diagnostic rate. A delay test can be performed.

〔Example〕

Next, the configuration and operation of one embodiment of the present invention will be sequentially described in detail with reference to FIGS.

In FIG. 1, a latch 1 is a latch for holding data constituting an LSI, and has an OS (only scan).
A clock can be applied to the latch 1 or the application can be suppressed according to the data set by scanning into the latch 2. Here, the sixteen latches 1 are classified into four, and are configured to scan / into OS (1) to OS (4) and apply / suppress a clock according to data set.

Here, the OS latch 2 is composed of OS (1) to OS (3).
It is configured to supply data set by scan-in to the corresponding latch 1 to apply a clock to the latch 1 or to suppress application of the clock. Here, OS (1) and OS (3) are set to “0” (valid value), and clock CLK1 is applied to source latch 1-1 on the first row and clock CLK2 is applied to target latch 1-2 on the third row. Application is enabled, and on the other hand, "1" (invalid value) is set in OS (2) and OS (4) to suppress application of the clock to the latches 1 in the second and fourth rows. Therefore, the activation of the state propagation path is not destroyed by the application of the clocks CLK1 and CLK2 at the position shown in FIG.

Next, according to the order shown in the flowchart of FIG.
The operation of the diagram configuration will be described in detail.

In FIG. 2, the path to be tested is determined. This determines the path on which the delay test shown using the bold line in FIG. 1 is to be performed. With this pass decision,
The source latch 1-1 and the target latch 1-2 are determined.

Scans and sets the OS latch 2 corresponding to the source latch 1-1 and the target latch 1-2 to valid values,
The other OS latch 2 is scanned in and set to an invalid value. This is because the OS (1) corresponding to the first row of the source latch 1-1 and the OS (3) corresponding to the third row of the target latch 1-2 shown in FIG. Set,
The other OSs (2) and (4) are scanned in and set to the invalid value “1”.

Changes the rising edge: After scanning in “0” in the source latch 1-1 and setting “1” in the input terminal of the source latch 1-1, the clock CLK1 is changed to the source latch.
The signal is sent to the target latch 1-2 by transmitting "1" to the output. When the falling edge is changed, "1" may be scanned into the source latch 1-1 and "0" may be scanned into the input terminal of the source latch 1-1 for setting.

Applies a clock CLK2 to the target latch 1-2 after a predetermined time has elapsed, and takes in data.

Determines whether the value of the target latch 1-2 is "1". In the case of YES, the data is propagated from the source latch 1-1 to the target latch 1-2 and taken in, so that it is determined that the delay is normal. On the other hand, if NO, the delay is determined to be abnormal (NG).

As described above, the valid value is scanned into the corresponding OS latch 2 and the application of the clock to the latch 1 other than the source latch 1-1 and the target latch 1-2 is suppressed, and the source latch 1-1 is switched to the target latch. By performing the data delay test on the latches 1-2, it is possible to prevent the activation condition from being destroyed during the delay test, and to perform the delay test with high accuracy and a high diagnostic rate.

 FIG. 3 shows a configuration diagram of one embodiment of the present invention.

In FIG. 3, OSLs (only scan latches) 1 to OSL4 are OS latches 2.

Source latch 1-1 and target latch 1-2 are OSL1, OS
Because the valid value “0” is scanned in and set to L3,
The clock CLK1 and the clock CLK2 are set to be applied respectively. Since the invalid value “1” is set in OSL2 and OSL4 by scanning in, the latch 1 corresponding to these is set.
The application of the clock to is suppressed. The behavior of this is
As in FIG. 1, (1) valid values “0” and
Scan in invalid value “1” into OSL2 and OSL4 and set them.
(2) Scan in and set “0” (or “1”) in the source latch 1-1 and set “1” (or “0”) in the input terminal. (3) Source latch the clock CLK1
The clock CLK2 is applied to the target latch 1-2 after a lapse of a predetermined time. At this time, target latch 1
When the data taken into -2 is "1" (or "0"), the delay is determined to be normal, and when it does not change, the delay is determined to be abnormal.

〔The invention's effect〕

As described above, according to the present invention, the delay test is performed in a state where the clock is applied to the latches 1 other than the source latch 1-1 and the target latch 1-2 by scanning into the OS latch 2. Is adopted,
The activation conditions during the delay test are prevented from being destroyed, and the delay test can be performed in a short time with high accuracy and a high diagnostic rate.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the principle of the present invention, FIG. 2 is a flowchart for explaining the operation of the present invention, FIG. 3 is a block diagram of an embodiment of the present invention, and FIG. In the figure, 1 indicates a latch, 1-1 indicates a source latch, 1-2 indicates a target latch, and 2 indicates an OS latch.

Claims (1)

(57) [Claims] In a clock control circuit for controlling a clock for performing a delay test, a latch (1) for holding data constituting an LSI is divided into a plurality of latches (1), and a clock is applied / suppressed to the divided latches (1). The OS latch (2) provided to control the delay time, and the OS latch (2) corresponding to the source latch (1-1) and the target latch (1-2) for which the delay test is to be performed, have valid values. Means for scanning in to and setting a clock; applying a clock to the source latch (1-1) to propagate its output; applying a clock to the target latch (1-2) after a predetermined time has elapsed; And a delay test clock control circuit.