JP2552103B2 - Semiconductor integrated circuit - Google Patents

Description

TECHNICAL FIELD The present invention relates to improvement of test mode setting of a semiconductor integrated circuit such as a microcomputer.

[Prior art]

A semiconductor integrated circuit including a ROM, a RAM, a decoder circuit and the like such as a microcomputer requires a test mode for testing the internal circuit in addition to a normal operation mode for performing a normal operation. In order to set the test mode, in addition to the original input / output terminals including the power supply terminal, a test terminal for determining the test mode has been conventionally required.
This test terminal is used only at the wafer test stage,
After assembly and mounting, it may not be released to the outside, but in such a case, the problem remains that complete testing in the final stage becomes difficult. In addition, when mounting the test terminals to the outside, the test can be completed completely up to the final stage, but the test terminals that are originally not necessary to fulfill the functions of the integrated circuit are valuable pins after mounting. Monopoly, especially
With a small number of mounting packages such as 14-pin and 16-pin, there was a drawback that the limited number of pins could not be effectively used for all pins for test terminals.

[Problems to be Solved by the Invention]

The present invention solves such a problem, and an object thereof is to provide a semiconductor integrated circuit capable of determining a test mode without providing a dedicated test terminal.

[Means for solving the problem]

A semiconductor integrated circuit according to the present invention is a semiconductor integrated circuit that selects a normal operation mode or a test mode according to a signal supplied from the outside, and a reset terminal to which a reset signal for initializing the semiconductor integrated circuit is input, A clock input terminal to which a clock signal for operating the semiconductor integrated circuit is input, and a signal input from the reset terminal is connected to a clock input section of each stage, and a signal input from the clock input terminal is input to the first stage of data. Connect to the
The output of each stage of the shift register is predetermined by inputting the output of each stage of the shift register of the plurality of stages and the shift register of the plurality of stages in which the output of each stage is sequentially connected to the data input section of the next stage. It is characterized by having a logic circuit for generating a signal for selecting the test mode when the output value is obtained.

〔Example〕

Hereinafter, the present invention will be described in detail based on examples.

FIG. 1 shows an embodiment of the present invention. In the figure, reference numeral 1 is a semiconductor integrated circuit, 2 is a clock input terminal, and a signal applied thereto is a gate circuit 6 composed of two stages of inverters.
Is supplied to the inside of the integrated circuit as a clock signal 9 and is connected to the first stage data input section of the shift register 4, which is a part of the constituent elements of the present invention. On the other hand, 3
The signal at the reset input terminal is supplied as a reset signal 10 for initializing the inside of the integrated circuit via the gate circuit 7, and is also connected to the clock input section of each stage of the shift register 4. In this example, the shift register has four stages, and the output of each stage and the reset signal 10 are connected to the input of the logic circuit 5 which determines the test mode, which is a component of the present invention. In this example, the logic circuit is composed of a 5-input NAND circuit and an inverter. The output 8 of the logic circuit 5 is uniquely determined by the state of the shift register 4, and here the code of the shift register is (0,1,1,0) and the reset signal 9
Is 1, the output 8 of the logic circuit 5 becomes 1 to enter the test mode. The timing diagram of FIG. 2 shows the timing of the reset input signal 3 and the clock input signal 2 when the semiconductor integrated circuit is initialized in the normal operation mode without selecting the test mode. 1 and 0 are always repeated in a certain cycle, the reset input signal 3 maintains the level of 1 for a certain period of time and then returns to the level of 0, and the integrated circuit starts the operation.

At this time, the state of the shift register is indefinite, but during the normal operation in which the reset input signal 3 is at the level of 0, the test mode signal 8 cannot be at the level of 1, and the test mode signal 8 is not entered into the test mode.

The timing diagram of FIG. 3 shows the waveforms for entering the test mode with the arrangement of the present invention. The clock input signal 2 becomes the input data of the shift register 4, and the reset signal 3
Becomes the clock input of the same shift register, and the waveform of the shift register causes the state of the shift register to become (0,1,1,0). If the reset signal 3 is 1, the output 8 of the logic circuit 5 is It becomes level 1 and enters the test mode.

〔effect〕

As described above, the shift register having a plurality of stages and the logic circuit having the outputs of the respective stages of the shift register as inputs are used as components, and the clock input normally used in the semiconductor integrated circuit is connected to the data input section of the shift register to reset. By connecting the input to the clock input of the same shift register, it is possible to test the integrated circuit without providing the conventionally required test input terminals, and all pins of the mounted product are used as terminals to perform the original functions. The effect of being able to do was obtained.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention. FIG. 2 is a timing chart showing the original usage in the embodiment of FIG. FIG. 3 is a timing chart for obtaining the effect in the embodiment of FIG. 1 ... Semiconductor integrated circuit 2 ... Clock input terminal 3 ... Reset input terminal 4 ... Shift register 5 ... Logic circuit 6 ... Clock input gate circuit 7 ... Reset input gate circuit 8 ... Test mode output 9: Internal clock signal 10: Internal reset signal

Claims (1)

(57) [Claims] 1. A semiconductor integrated circuit that selects a normal operation mode or a test mode according to a signal supplied from the outside, a reset terminal to which a reset signal for initializing the semiconductor integrated circuit is input, and the semiconductor integrated circuit. A clock input terminal to which the operation clock signal is input, and a signal input from the reset terminal is connected to the clock input section of each stage, and a signal input from the clock input terminal is connected to the data input section of the first stage. However, the output of each stage of the shift register is determined in advance by inputting the output of each stage of the shift register of the plurality of stages and the shift register of the plurality of stages in which the output of each stage is sequentially connected to the data input section of the next stage. A semiconductor integrated circuit having a logic circuit for generating a signal for selecting the test mode when the output value reaches a predetermined value.