JPH0830730B2 - Test mode setting circuit in semiconductor integrated circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a test mode setting circuit in a semiconductor integrated circuit including a logic circuit and the like, and in particular, one test mode setting circuit generates a test mode setting signal. The present invention relates to a test mode setting circuit in a semiconductor integrated circuit.

[Prior Art] In the manufacture of a conventional semiconductor integrated circuit, a test mode setting circuit is provided in the same semiconductor integrated circuit in order to inspect an internal logic circuit or the like in a manufacturing process, and the test mode setting circuit is externally provided. Controlled from, various test mode signals are generated.

This test mode signal is input to an internal logic circuit, etc., and is applied to the determination of normality / abnormality from the response state and to search for an abnormal portion. Today, in the era of the peak of semiconductor integrated circuits, complicated semiconductor integration It is an essential circuit for efficient mass production of circuits.

Next, a conventional test mode setting circuit in a semiconductor integrated circuit will be described with reference to a circuit diagram.

 A conventional circuit is shown in FIG.

Description of Circuit Configuration: In FIG. 3, a semiconductor integrated circuit 1 comprises an input terminal A, an internal logic circuit 5, an output terminal B, and an intermediate potential detecting means 2.

The intermediate potential detecting means 2 is a high level threshold inverter.
21 and low level threshold inverter 22 and inverter 23 and AN
A test mode setting circuit composed of D24 and outputting a test mode setting signal.

The relationship between the input voltage of the inverters 21-23 and the logic level is shown in FIG.

Description of circuit operation: When setting the test mode of the internal logic circuit of this semiconductor integrated circuit; a normal logic level signal (1 or 0) is applied to the input terminal A.
A signal having a different level from is input to the input terminal A.

In other words, when the logic input terminal and the signal input terminal for test mode setting are shared by the input terminal A and the intermediate potential signal (1/2 V) is input to the input terminal A, the test mode setting circuit is When operated and a logic level signal other than the intermediate potential is input, the normal internal logic circuit operates normally.

When the intermediate potential signal is input to the input terminal A, the high level threshold inverter 21 of the test mode setting circuit 2
(Threshold voltage> 1/2 V) and low level threshold inverter 22 (threshold voltage <1/2 V).

When the intermediate potential signal is input to the high-level threshold inverter 21, the input potential is lower than the threshold voltage, so that the high-level threshold inverter 21 determines that the logic level is 0, the output is inverted, and the logic level 1 signal is converted to AND24. Is output to.

When the intermediate potential signal is input to the low-level threshold inverter 22, the input potential is higher than the threshold voltage, so that the low-level threshold inverter 22 is determined to be at the logic level 1, and the output is inverted and the logic level 0 signal is output. It is output to the inverter 23.

The logic level 0 signal input to the inverter 23 is inverted and the logic 1 signal is output to the AND 24.

AND24 performs AND24 of the logic level 1 signal output from the high level threshold inverter 21 and the logic level 1 signal output from the inverter 23 to obtain the logic level 1
Output signal C is output.

This output signal C is used as a test mode setting signal for the internal test circuit. If the output of AND24 is logic level 0, the test mode is not entered.

The above has described the case where the test mode setting circuit 2 is operated in the test mode.

Only one state of the test mode setting signal set by this circuit can be output, that is, when the logic output is 0, it is in the non-test mode setting state, and when it is 1, it is one test mode setting state. Represents

[Problems to be Solved by the Invention] In the conventional circuit, the testable range is limited because only one type of test mode setting signal can be output.

It has been desired to have a circuit that can generate a plurality of different test mode setting signals for testing in various modes.

It is an object of the present invention to provide a test mode setting circuit capable of generating a plurality of different test mode setting signals in a test mode setting circuit of a semiconductor integrated circuit.

[Means for Solving the Problems] In view of the above problems, the present invention has improved the conventional test mode setting circuit in order to achieve the object.

In other words, in a semiconductor integrated circuit including a multi-stage register whose stored contents sequentially change according to a clock input, a test mode setting circuit in the semiconductor integrated circuit that generates a test mode signal for the internal logic circuit, Clock input is made possible by an intermediate potential detecting means for detecting an intermediate potential between a logic 1 level signal and a logic 0 level signal inputted to an input terminal, and a detection signal outputted from the intermediate potential detecting means, and A test mode setting flip-flop for inputting a signal output from the final stage of the multi-stage register, a signal output from the flip-flop, and a test mode signal according to the output from the register of each stage of the multi-stage register. Output test mode selection means, and further, the input of the intermediate potential detection means is connected. When a logic level signal potential other than the intermediate potential is applied to the input terminal for the subsequent internal logic circuit, the flip-flop is reset by the signal output from the intermediate potential detecting means. And

[Operation] In the present invention, the multistage register of the logic circuit in the semiconductor integrated circuit is used, and the output of the multistage register is used to generate the corresponding test mode setting signal. That is, the larger the number of stages of the multi-stage register, the more kinds of test mode setting signals can be generated.

[Examples] Examples of the present invention will be described below.

 FIG. 1 is a circuit diagram showing an embodiment of the present invention.

Description of Circuit Configuration: In FIG. 1, the semiconductor integrated circuit 1 has an input terminal A,
C, D, internal logic circuit 5, and test mode setting circuit 8
Composed of.

The test mode setting circuit 8 includes the intermediate potential detecting means 2 and
It is composed of an AND3, an inverter 7, a flip-flop 4, and a test mode selection means 6.

The intermediate potential detecting means 2 is composed of the same circuit as the conventional one,
It is composed of a high level threshold inverter 21, a low level threshold inverter 22, an inverter 23, and an AND 24.

The test mode selection means 6 is composed of AND 61 to 64.

The internal logic circuit 5 includes registers 51 to 54. The outputs from the respective registers are output to the test mode selecting means 6, and the final stage register output is also output to the flip-flop 4.

The clock input to the input terminal C is registered in the registers 51 to 54.
And a logic 1 signal (a signal for setting the test mode) output from the intermediate potential detecting means 2 and is gated by the AND 13 and output to the flip-flop 4.

The signal output from the flip-flop 4 is output to AND 61 to 64 of the test mode selection means, and the signal output from the registers 51 to 54 is AND gated and output by this signal.

Description of circuit operation: In FIG. 1, when the test mode is set; data is input to the input terminal A, a clock is input to the input terminal C, and an intermediate potential is input to the input terminal D. .

During the test mode setting, it is necessary to input the intermediate potential to the input terminal D.

When the above preparation is completed, the operation for generating the test mode setting signal is started.

That is, the timing chart (A) shown in FIG.
The operations of (B), (C), and (D) are performed, and finally the first
Test mode setting signals of different combinations are output from the tests 1, 2, 3, and 4 in the figure.

When the intermediate potential is input to the input terminal D, the intermediate potential detection means 2 performs the conventional operation, and the logic level 1 is output to AND3.

With this logic level 1 output, the AND3 input terminal C
The clock input to is ANDed and the input clock is output to the flip-flop 4.

The data input to the input terminal A is input to the register 51, and the data shifted corresponding to the input clock is
It is output to the register 52.

Similarly, in the registers 53 to 54, the data is similarly shifted, and the output data is output to the test mode selecting means 6 respectively.
It is output to AND 61 to 64 of.

The data output from the register 54 at the final stage is also output to the flip-flop 4.

The flip-flop 4 transfers the data output from the register 54 to the AND 61 to 64 when the signal output from the inverter 7 is at the logic level 0 by the clock output from the AND 3.

Here, the relationship among the input data, the clock, the outputs of the registers 51 to 54, and the output of the flip-flop 4 is shown in FIG.

In FIG. 2 (A), the test signal generating pulse is output from the flip-flop 4 to the ANDs 61 to 64 at the fifth clock, and as the AND outputs (test 1 output,
Test 2 output, test 3 output, test 4 output) is (1,
The signal 0, 0, 0) is output.

When the input data is changed, a signal (0, 1, 0, 0) is output in FIG. 2 (B), and a signal (0, 0, 1, 0) is output in FIG. 2 (C). A signal is output, and in FIG. 2 (D), (0, 0, 0, 1)
Is output.

In this way, by changing the input data,
Different test mode setting signals are generated.

The test signals thus generated generate test data of different modes and are used as signals for testing the internal logic circuit.

When the test mode is not set; input terminals A, C and D have normal logic level signals (1,
By inputting 0), the internal logic circuit can be operated.

Further, in the test mode setting circuit 8, when the input logic level of the input terminal D is 0 or 1, the output of the intermediate potential detecting means 2 is set to the logic level 0, so that the output of the inverter 7 is set to the logic level 1. Since the flip-flop 4 is reset by this output, it is not output from the flip-flop 4 either, so that the test mode setting signal is not output.

[Effects of the Invention] As described above, according to the present invention, it is possible to generate different combinations of signals in the test mode setting circuit by utilizing the registers of the internal circuit, so that signals of different patterns are used in the internal circuit. Can be tested.

Therefore, it is clear that the reliability and quality of the semiconductor integrated circuit are improved and maintained, and the economical efficiency is greatly improved.

[Brief description of drawings]

1 is a circuit diagram showing an embodiment of the present invention, FIG. 2 is a timing chart, FIG. 3 is a conventional circuit diagram, and FIG. 4 is a definition of input voltage and logic level of the inverters 21-22. It is a figure. 1 ... Semiconductor integrated circuit 2 ... Intermediate potential detection means 3,24,61 to 64 ... AND 4 ... Flip-flop 5 ... Internal logic circuit 6 ... Test mode selection means 7,23 ... Inverter 8 ... Test mode setting circuit 21 …… High level threshold inverter 22 …… Low level threshold inverter 51 to 54 …… Register

Claims (2)

[Claims] 1. A test mode setting circuit in a semiconductor integrated circuit for generating a test mode signal for an internal logic circuit in a semiconductor integrated circuit including a multi-stage register, the contents of which sequentially change in response to a clock input. Clock input is possible by means of an intermediate potential detecting means for detecting an intermediate potential between a logic 1 level signal and a logic 0 level signal inputted to an input terminal for a circuit, and a detection signal outputted from the intermediate potential detecting means. And a test mode setting flip-flop for inputting a signal output from the final stage of the multi-stage register, a signal output from the flip-flop, and a test according to the output from the register of each stage of the multi-stage register. A test mode selecting means for outputting a mode signal, and a test mode in a semiconductor integrated circuit comprising: Setting circuit. 2. The intermediate potential detection according to claim 1, wherein a logic level signal potential other than the intermediate potential is applied to the input terminal for the internal logic circuit to which the input of the intermediate potential detecting means is connected. A test mode setting circuit in a semiconductor integrated circuit, comprising means for resetting the flip-flop according to a signal output from the means.