JP2947168B2 - Semiconductor integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit forming a scan path circuit functioning as a shift register circuit by cascading a plurality of flip-flop circuits in an integrated circuit.

[0002]

2. Description of the Related Art For a conventional scan path circuit of this kind, reference is made to, for example, Japanese Patent Application Laid-Open No. 3-65671.

Conventionally, this type of semiconductor integrated circuit forms a scan path circuit that operates as a shift register by cascade-connecting a plurality of (n) flip-flop circuits in the semiconductor integrated circuit during a test, and forms a scan path circuit from an external terminal. A test signal is input, and the operation result of the combinational circuit unit is read out via a flip-flop formed as a shift register, thereby increasing the capacity of the test.

[0004]

In the above-mentioned conventional semiconductor integrated circuit, a plurality of flip-flop circuits are cascade-connected, and a test pattern signal is sequentially sent from the first-stage flip-flop circuit to each flip-flop circuit. Is set to the data.

When observing the internal state, a signal sequentially output from the last flip-flop circuit is observed using a scan path circuit.

Therefore, when there is a failure in a part of the scan path circuit, predetermined data is set,
Observation becomes impossible, and as a result, there is a problem that an expected test cannot be performed or satisfactory failure data cannot be collected. In other words, the conventional method has a problem in that even if there is a failure in a part of the scan path circuit, the failure location cannot be specified.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and has as its object to provide a semiconductor integrated circuit capable of easily specifying a fault location in a scan path circuit of the semiconductor integrated circuit. I do.

[0008]

In order to achieve the above object, a semiconductor integrated circuit according to the present invention is configured as a scan path circuit in which a plurality of flip-flop circuits are connected in cascade and can be operated as a shift register circuit. In a semiconductor integrated circuit, during a test, a scan output of a flip-flop constituting the scan path circuit is set to a desired value selected by an externally input signal.
By doing, the flip-flop and scan output of the subsequent stage
The terminal is set to the above value .

[0009]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram corresponding to a test in an embodiment of the present invention. A plurality (n) of scan flip-flops 1-1 to 1-n form a shift register during a scan path test, and the scan input SI of the first-stage scan flip-flop 1-1 is supplied from the scan input terminal 11 to the scan input SI. Is input.

The scan output SO of the scan flip-flop of each stage is connected to the scan input SI of the next stage.

Last stage scanning flip-flop 1-
The n scan outputs SO are output from the scan output terminal 15.

Each flip-flop 1-1-1 for scanning
The signal from the clock input terminal 12 is connected to the -n clock input C, the signal from the set input terminal 13 is connected to the set input S, and the signal from the reset input terminal 14 is connected to the reset input R.

FIG. 2 is a diagram for explaining one embodiment of the present invention, and shows a configuration example of the scanning flip-flop 1. In FIG. Referring to FIG. 2, inverted output Q # of flip-flop 2 is connected to the input terminal of inverter 5 and also to the connection point of p-channel MOS transistor 3 and n-channel MOS transistor 4.

The source of n-channel MOS transistor 4 is connected to ground potential GND, and the source of p-channel MOS transistor 3 is connected to power supply potential VDD. A reset input R is connected to the gate input of the p-channel MOS transistor 3, and a set input S is connected to the gate input of the n-channel MOS transistor 4.

Next, the operation of the flip-flop circuit shown in FIG. 2 will be described.

When the set input S is "0" and the reset input R is "1", both the p-channel MOS transistor 3 and the n-channel MOS transistor 4 are turned off,
The signal of inverted output Q # of flip-flop 2 is inverted by inverter 5 and data Q in flip-flop 2 is output to scan output SO.

When the set input S is "1" and the reset input R is "1", the p-channel MOS transistor 3 is turned off, the n-channel MOS transistor 4 is turned on, and the input of the inverter 5 is set to "0". "(Low level), and the flip-flop 2
"1" is output irrespective of the data inside.

When the set input S is "0" and the reset input R is "0", the p-channel MOS transistor 3 is turned on, the n-channel MOS transistor 4 is turned off, and the input of the inverter 5 is set to "1". ”(High level), and“ 0 ”is output to the scan output SO regardless of the data in the flip-flop 2.

Next, the operation during the scan path test will be described with reference to FIG.

When a clock signal is input from the clock input 12 in a state where "0" is input to the scan input terminal 11, "0" is input to the reset input terminal 14, and "0" is input to the set input terminal 13, the flip-flop for all scans 1-1-1
As for -n, "0" is set at the same time. When the reset input terminal 14 is set to "1" in this state, the shift register operates as a normal shift register. Therefore, if a clock signal is input n times, the scan output SO, that is, the data "0" held in each scan flip-flop is output from the scan output terminal 15. "Can be observed sequentially.

On the other hand, when a clock signal is input from the clock input 12 with "1" input to the scan input terminal 11, "1" input to the reset input terminal 14, and "1" input to the set input terminal 13, all scan flip-flops 1-1
.About.1-n are simultaneously set to "1". When the reset input terminal 13 is set to "0" in this state, the circuit operates as a normal shift register. Therefore, if a clock signal is input n times, the data "1" held in each scan flip-flop is sequentially observed from the scan output terminal 15. can do.

If there is a failure in a part of the scan path circuit, the scan output S is started during the above operation.
The value of O, that is, the output value of the scan output terminal 15 becomes a failure.

At this time, by finding the number of clocks input before the incorrect data is output, a failed flip-flop can be specified in the scan path.

[0025]

As described above, according to the present invention,
In the scan path test, the data of flip-flops on the scan path can be set to “0” or “1” simultaneously by the external input terminal, so that if there is a failure on the scan path, the failure location can be easily specified. It has the effect that it can be done.

Further, according to the present invention, since the test circuit is added only to the scan output, the characteristics during normal use are not affected.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a test according to an embodiment of the present invention.

FIG. 2 is a diagram for explaining an embodiment of the present invention, and is a diagram showing a configuration of a flip-flop with a scan path function.

[Explanation of symbols]

 1-1 to 1-n scan flip-flop 2 flip-flop 3 p-channel MOS transistor 4 n-channel MOS transistor 5 inverter 11 scan input terminal 12 clock input terminal 13 set input terminal 14 reset input terminal 15 scan output terminal

Claims (1)

(57) [Claims] 1. A semiconductor integrated circuit configured as a scan path circuit in which a plurality of flip-flop circuits are connected in cascade and can be operated as a shift register circuit, wherein a scan is performed on each output stage of the plurality of flip-flops. Examples use output, and an output, wherein the flip-flop holds, one of the set and / or reset state, a selection means for selectively outputting the signals inputted from the outside, the test starting at, by the selection means Multiple flits
The semiconductor integrated circuit, characterized in that each scan output of the flop becomes configured to set the desired identity value.