JP2697691B2 - Semiconductor integrated circuit having scan path - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor integrated circuit having a scan path, and more particularly to a semiconductor integrated circuit having a shift register type scan path.

[0002]

2. Description of the Related Art An increase in the scale of a circuit integrated on a single semiconductor chip has made it difficult to test the semiconductor chip. Therefore, a scan path method has been proposed for the purpose of facilitating the test.

[0003] Above all, a scan path of a shift register system (that is, flip-flops in an LSI are connected like a shift register, a test signal is input from the outside, and the operation result of the combinational circuit section is read out to facilitate the test). 4), as shown in FIG. 4, a method in which a latch provided in a data path for transferring normal data and a latch provided in a scan path for transferring test data are used effectively is to effectively use the circuit. It is in the spotlight.

Referring to FIG. 4, two inverters 1, 2
The input terminal and the output terminal are connected to each other, and the latch includes a data path composed of clocked inverters 3 and 4 controlled by normal data transfer clocks φ￣ and φ, respectively, and a scan test. Clock φ _T ￣,
It is connected to the node A in such a form that it is used for both the scan path controlled by φ _T. Note that clock φ￣ is a complementary signal of clock φ, and symbol “￣” indicates inversion.

The operation of the circuit shown in FIG. 4 will be described below.

At the time of normal data transfer, clocks φφ and φ are activated, data transferred via a data path is held in a latch, and data held in the latch is controlled by clock φ to the next stage ( (Not shown). During this time, the scan test clocks φ _T , φ _T ￣ (inverted) are inactive. More specifically, when the data transfer clock φ changes from the high level to the low level, the clocked inverter 3 is turned off, the latch is separated from the data D and holds the data, and the data transfer clock φ is changed from the low level to the high level. When the level changes to the level, the data held in the latch from the clocked buffer 4 is inverted, and at this time, both the clocked inverters 5 and 6 are turned off.

On the other hand, at the time of the scan test, the clock φ _T反 転 (inversion) and φ _T are activated, and the data S for the scan test passes through the scan path including the clocked inverter 5, contrary to the normal data transfer. Input to the latch via
Data of this latch is transferred from the clocked inverter 6 receives the control of the clock phi _T to the next scan path (not shown).

With such a circuit configuration, it is possible to use both the latch of the normal data and the latch of the scan test data, and the number of circuit elements is reduced.

[0009]

However, in the above-described conventional scan path circuit, the following disadvantages have become remarkable by also using the latch circuit.

That is, regarding the node A to which the dual-purpose latch is connected, the clocked inverter 4 for the data path and the clocked inverter 6 for the scan path function as load capacitances. Become.

That is, referring to FIG. 6, when the load capacities of the two inverters 4 and 6 are C ₁ and C ₂ , a combined capacity C ₁ + C ₂ is connected to node A, and the node A is charged and discharged. That is, as shown in FIG. 5, the rising characteristic of the node A is deteriorated. In FIG. 6, a resistor R indicates an on-resistance of an output stage transistor of the clocked inverter 3, and a node A
Is pulled up to the power supply potential _VDD or the ground potential GND via the resistor R. FIG. 5 shows the signal waveform of each node in FIG. 4. D is a data signal input to the clocked inverter 3, A is the potential of the node A, and C is the output potential of the inverter 2 constituting the latch. ing.

As a result, as shown in FIG. 5, the setup speed (setup time) of the latch is reduced, and as a result, the operating speed of the integrated circuit during normal data transfer is limited, and it is not possible to cope with the increase in speed. Has occurred.

Accordingly, the present invention solves the above-mentioned problems and provides a semiconductor device having a scan path which can significantly reduce the setup time of the latch during normal data processing while using both the data path latch and the scan path latch. It is an object to provide an integrated circuit.

[0014]

To achieve the above object, the present invention provides a semiconductor integrated circuit having a scan path of a shift register system, wherein the scan path and a normal data path are connected via a resistance means. A latch shared by both the scan path and the data path,
A semiconductor integrated circuit having a scan path connected to the data path side is provided.

According to the present invention, preferably, the latch is provided between the first and second switch elements provided on the data path, and a control clock for controlling data holding and transfer timings is input to a control terminal. And third and fourth switch elements, on the scan path, to which control clocks for controlling data holding and transfer timings at the time of a scan path test are input to control terminals, respectively, are provided. The resistance means is connected between a connection point with a path and the scan path between the third and fourth switch elements.

Further, the present invention is preferably characterized in that the resistance means comprises an on-resistance of a MOS transistor.

[0017]

According to the present invention, the latch is connected to the scan path via the resistor according to the present invention, so that the apparent load at the time of data transfer can be reduced, and as a result, the setup time can be reduced. Can be speeded up.

[0018]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a diagram showing the configuration of one embodiment of the present invention.

Referring to FIG. 1, input terminals and output terminals of inverters 1 and 2 are mutually connected to node A of a data path having clocked inverters 3 and 4 controlled by clocks φ￣ and φ. The latch is connected. Node A is a MOS transistor 7 or 8 functioning as a resistance element.
Connected to the scan path.

The scan path includes clocked inverters 5, 6 controlled by clocks φ _{T T} , φ _T , respectively.

The gate terminals of the P-channel MOS transistor 7 and the N-channel MOS transistor 8 whose source and drain are commonly connected to each other are connected to the ground potential, respectively.
GND and the power supply potential _VDD , the two MOS transistors 7 and 8 are always in a conductive state, and their on-resistance plays a role of electrically separating the data path and the scan path by a resistance component.

If the resistance value of the on-resistance is too high, the scan path and the latch become electrically insulated, and
Since the scan test cannot be performed, the resistance value of the ON resistance of the MOS transistors 7 and 8 is set to a value that does not hinder the operation.

In the present embodiment, by adopting the circuit configuration shown in FIG. 1, the load capacity for the latch is reduced during normal data transfer, and the rising characteristics of the node A and the rising characteristics of the node B on the scan path are reduced. And a difference. That is, as shown in FIG. 3, the node A load capacitance C ₂ of the clocked inverter 6 is connected through an on-resistance R2 of the MOS transistors 7 and 8,
Only the load capacitance C ₁ of the clocked inverter 2 is connected directly to the contact A to the node A. In FIG. 3, the resistor R1 connected to the node A indicates the on-resistance of the output stage transistor of the clocked inverter 3, and the node A indicates the resistor R
It is pulled up to the power supply potential V _DD side or pulled down to the ground potential side via 1.

The node A on the data path to which the latch is directly connected can be instantaneously raised or lowered by the resistive voltage dividing operation (see FIG. 3).
As shown in (1), the setup time for latching the normal data can be shortened. FIG. 2 is a diagram showing a signal waveform at each node in FIG. 1, where D is a data signal input to the clocked inverter 3, A is the potential of the node A, B
Indicates the potential of the node B in the scan path, and C indicates the output potential of the inverter 2 forming the latch.

Referring to FIG. 2, the rise time of node A is faster than the rise time of node B. The potential difference between the rising points of the nodes A and B corresponds to the potential drop between the on-resistance R2 (see FIG. 3). The rising characteristic of the node B shown in FIG. 2 is substantially equal to the rising characteristic of the node A of the conventional example shown in FIG.

According to the present embodiment, according to the simulation, the integrated circuit driven by 5 V is 1.93 in the conventional example.
μs required setup time is reduced by about 10%,
It can operate with a setup time of 1.77 μs.

On the other hand, in this embodiment, when a scan path test is performed, the scan path is connected to the latch via the on-resistance of the MOS transistors 7 and 8,
Although the set-up speed is reduced, it is possible to reliably hold the scan data.

In general, the scan test does not require much speed (it can be slower than the normal operation), so even if the setup time becomes longer, there is no operational problem.

Although the present invention has been described with reference to the above embodiment, the present invention is not limited to the above embodiment, but includes various embodiments according to the principle of the present invention. For example, in the above embodiment, the clocked inverter is used. However, as long as the conduction and non-conduction can be controlled by the control clock, a transfer transistor, a tri-state buffer, or the like may be used. Although an example in which the ON resistance of a MOS transistor is used as the resistance element for connecting the MOS transistors is shown, the present invention is not limited to this, and includes various resistance elements formed on an integrated circuit such as a polysilicon resistance and a diffusion resistance. Of course.

[0030]

As described above, according to the present invention,
There is an effect that the setup time of the latch at the time of normal data processing can be significantly reduced while the latch for the data path and the latch for the scan path are also used. As an example of the quantitative effect of the present invention, according to a simulation, in a 5V-driven integrated circuit, a conventional 1.93 μm
The required setup time can be reduced by about 10% 1.
77 μs can be set.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of an embodiment of the present invention.

FIG. 2 is a diagram showing a timing waveform according to an embodiment of the present invention.

FIG. 3 is a diagram showing an equivalent circuit for schematically explaining one embodiment of the present invention.

FIG. 4 is a diagram showing a conventional example.

FIG. 5 is a diagram showing a timing waveform of a conventional example.

FIG. 6 is a diagram showing an equivalent circuit for schematically explaining one embodiment of the present invention.

[Explanation of symbols]

1-6 Inverter 7 P-type MOS transistor 8 N-type MOS transistor D Normal data path input S Scan path input φ, φ￣ (inverted) Normal data transfer clock φ _T , φ _T ￣ (inverted) Scan path clock

Claims (3)

(57) [Claims] 1. A semiconductor integrated circuit having a scan path of a shift register system, wherein the scan path and a normal data path are connected via a resistance means, and a latch used for both the scan path and the data path is provided. Is connected to the data path side, the semiconductor integrated circuit having a scan path. 2. The latch is inserted between first and second switch elements provided on the data path and receiving control clocks for controlling data holding and transfer timings, respectively, to a control terminal. On the scan path, there are provided third and fourth switch elements to which control clocks for controlling data holding and transfer timings at the time of a scan path test are input to control terminals, respectively, and a connection point between the latch and the data path. And the third,
2. The semiconductor integrated circuit having a scan path according to claim 1, further comprising a configuration in which said resistance means is connected between said scan path between fourth switch elements. 3. The semiconductor integrated circuit having a scan path according to claim 1, wherein said resistance means comprises an on-resistance of a MOS transistor.