JPH0750149B2 - How to test shift registers - Google Patents

Description

The present invention relates to a shift register test method used in a serial scan path test of a semiconductor integrated circuit, and for the purpose of detecting a short-circuit fault, n (n is an integer of 2 or more) flip-flops. In the test method of the shift register configured by connecting in series,
Test data having a logical value "1" or "0" and burst data having a logical value inverted with respect to the test data and at least (n-1) consecutive burst data are input to the shift register, and the test data is input. Are shifted by n including the input, and a failure is detected by the presence or absence of output of the test data from the shift register.

[Industrial application field]

The present invention relates to a shift register test method, and more particularly to a shift register test method used for a serial scan path test of a semiconductor integrated circuit.

A serial scan path test method is generally used for testing semiconductor integrated circuits. As shown in FIG. 5, this test method uses a flip-flop 11 ₁ in the semiconductor integrated circuit 10.
~ 11 _n are connected in series to form a shift register, scan-in the test signal to the shift register and set it to test the combinational circuit 12, and set the output of the combinational circuit 12 to the shift register. To scan out. In this method, the flip-flops 11 _{1 to} 11 _n are regarded as pseudo external input / output pins for testing, and the function of the shift register itself is not tested.

Therefore, it is necessary to test the operation of the shift register before applying the serial scan path test method.

[Conventional technology]

In the conventional shift register test, as shown in FIG. 6, "10" is supplied as the scan input of the terminal 16 together with the clock input of the terminal 15, and then the scan input is shifted by the clock input. After the nth clock input Terminal 17
It is checked whether the scan output of "1" is "1" and the scan output is "0" after the (n + 1) th clock input.

As a result, a "1" stuck-at fault such as one of the output terminals of the flip-flops 11 _{1 to} 11 _n being connected to the power supply Vcc and a "0" stuck-at fault such as being connected to the power supply GND can be determined.

[Problems to be solved by the invention]

As the degree of integration of the semiconductor integrated circuit increases, as shown in FIG. 7, the i−1 (1 <i <n) th flip-flop (F
F) There is an increasing possibility that a short-circuit fault occurs in which the output terminal of the 11 _i−1 output terminal j (1 <i <j <n) of the flip-flop 11 _j is short-circuited.

In the above short-circuit fault, the structure of the flip-flops 11 _{1 to} 11 _n causes the short-circuit point to exhibit an AND function, an OR function, etc., and forms a shift register loop having the short-circuit point as a starting point and an ending point.

As shown in FIG. 8A, when the output parts of the flip-flops 11 _{1 to} 11 _n are C-MOS inverters 20 and 21, a short circuit causes c1 = d1 = ▲ ▼ to show the OR function. Further, as shown in FIG. 7B, when signals are output from the n-channel MOS transistors 23 and 24, c2 = d2 due to a short circuit.
= Ad, indicating the AND function.

Further, as shown in FIG. 9 (A), the flip-flop 11 ₁
~ 11 _{n When} each output section uses the npn transistors 25 and 26 of the emitter follower, due to a short circuit, c3 = d3 = a3 + b3
Indicates the OR function. Further, as shown in FIG. 7B, when the grounded emitter npn transistors 27 and 28 are used, a short circuit results in c4 = d4 = a4.b4, which indicates the AND function.

As described above, the short circuit fault cannot be detected by the conventional test for detecting the stuck-at fault.

The present invention has been made in view of the above points, and an object thereof is to provide a shift register test method capable of detecting a short-circuit fault.

[Means for solving problems]

Test method for the shift register of the invention, n (n is an integer of 2 or more) in the flip-flops (11 ¹ to 11 _n) test method of a shift register constructed by cascading the logical value in the shift register At least (n-1) continuous burst data of "1" or "0" is shift-input, test data whose logical value is inverted with respect to the burst data is shift-input, and the setting data of the shift register is ( n-1) shifting, and detecting a failure depending on whether or not the test data is output from the shift register.

In a test method of a shift register configured by cascade-connecting n (n is an integer of 2 or more) flip-flops (11 ^{1 to} 11 _n ), the n flip-flops are preset to a logical value “1”. Alternatively, it is cleared to a logical value “0”, the test data whose logical value is inverted with respect to the preset or clear is shift-input, the setting data of the shift register is shifted by (n−1), and the A failure is detected depending on whether or not the test data is output.

Also, in a test method of a shift register configured by cascade-connecting n (n is an integer of 2 or more) flip-flops (11 ^{1 to} 11 _n ), a logical value of “1” or “0” is assigned to the shift register. The test data is shift-input, the logical value is inverted with respect to the test data, and at least (n-1) continuous burst data is shift-input, and a failure is caused depending on whether the test data is output from the shift register. To detect.

[Action]

In the present invention, the test data and the burst data are input, the test data is shifted by n, and the failure is detected by the presence or absence of the output of the test data from the shift register.

If the shift register has a stuck-at fault or a short-circuit fault, the test data is destroyed, so that the above fault can be detected.

〔Example〕

4A and 4B show flip-flops (FF) 11 ₁ to 1
1 shows a short-circuit failure model in which output terminals of flip-flops 11 _i-1 and 11 _{j of} a shift register in which 1 _n are cascaded are short-circuited.

In FIG. 4 (A), the flip-flops 11 _{1 to} 11 _n are configured as shown in FIG. 8 (B) and FIG. 9 (B), and the short-circuit point has an AND function.
FIG. 4 (B) shows a model in which the flip-flops 11 _{1 to} 11 _n have the configuration shown in FIGS. 8 (A) and 9 (A) and the short-circuit point has the OR function 31. Is a model of.
In both models, the flip-flops 11 _{i to} 11 _j within the short circuit point form a shift register loop.

FIGS. 1A and 1B show the data structure of the first embodiment of the method of the present invention. Here, the logical value "0" supplied to the terminal 16 shown in FIGS. 4A and 4B is represented by "L", the logical value "1" is represented by "H", and "X" is shifted. Represents
Further, the subscripts represent the logical value and the order of shift.

In FIG. 1 (A), after shift input burst data of the flip-flops 11 ₁ to 11 _n number (n number of) only a logical value "0", the shift only one test data of a logical value "1" input After that, the shift is performed by (n-1). If there is a short circuit (AND short circuit) with AND function in the shift register, the logical value "0" circulates in the shift register loop.
After the supply of the test data, the output of the terminal 17 becomes the logical value "0", and the short-circuit fault shown in FIG. 4 (A) can be detected. In addition,
In the case of a "0" stuck-at fault, a logical value "0" is output and can be detected.

In FIG. 1 (B), after shift input the logic value "1" only flip-flop 11 ₁ to 11 _n number (n number of), shifted by one the logical value "0" input, then (n- Shift only 1). If the shift register has a short circuit having an OR function (OR short circuit), the logical value "1" circulates in the shift register loop, so that the output of the terminal 17 becomes the logical value "1" after the above test data is supplied. The short-circuit fault shown in B) can be detected. Even in the case of a "1" stuck-at failure, the logical value "1" is output and can be detected.

Therefore, the short-circuit fault and the stuck-at fault of the shift register can be detected by supplying the test data of FIG. 1 (A) and then the test data of FIG. 1 (B).

FIGS. 2A and 2B show the data structure of the second embodiment of the method of the present invention. This test data is flip-flop 11
_This is used when each of _{1 to} 11 _n has a clear input and a preset input. Instead of shifting n logical values “0” or “1” in FIG. 1 (A) and (B) respectively, L clear Or perform H preset.

Burst data of logical value "0" or "1" is set in the flip-flops 11 _{1 to} 11 _n by the above L clear or H preset. After that, it is exactly the same as each of FIG. 1 (A) and (B), and AND short circuit or “0” degeneracy is detected in the test data of FIG. 2 (A), and the test data of FIG. 2 (B) is detected. Detects OR short or "1" degeneration.

1 (A) and (B) and 2 (A) and (B).
(N-1) shifts in X _{n + 2} ... X _2n or X ₂
... When performing X _n , any logical value may be shift-inputted to the terminal 16.

FIGS. 3A and 3B show the data structure of the third embodiment of the method of the present invention.

In FIG. 3 (A), the test data of logical value "1" is set to 1
Only the number of the burst data having the logical value "0" is shift-input by (n-1). If there is an AND short circuit in the shift register, the logical value "0" circulates in the shift register loop.
The output has a logical value "0", and the short-circuit fault or "0" degeneracy shown in FIG. 4 (A) can be detected.

In FIG. 3 (B), the test data of logical value “0” is set to 1
Only the number of the burst data having the logical value "1" is shift-input by (n-1). If there is an OR short circuit in the shift register, the logical value "1" circulates in the shift register loop. Therefore, the output of the terminal 17 becomes "1" after supplying the test data, and the short circuit failure or the short circuit failure shown in FIG. "1" degeneration can be detected.

Therefore, after the test data of FIG. 3 (A) is supplied, the test data of FIG. 3 (B) can be supplied to detect the AND short circuit and the OR short circuit of the shift register.

〔The invention's effect〕

As described above, according to the method of the present invention, both the stuck-at fault and the short-circuit fault of the shift register can be detected, which is extremely useful in practice.

[Brief description of drawings]

1, 2, and 3 are diagrams showing the data structure of the first, second, and third embodiments of the method of the present invention, FIG. 4 is a diagram showing a short-circuit failure model, and FIG. 5 is a serial diagram. FIG. 6 is a diagram for explaining a scan path test, FIG. 6 is a configuration diagram of a shift register, FIG. 7 is a diagram showing a short-circuit fault, and FIGS. 8 and 9 are respectively a short-circuit AND function and an OR function. It is a circuit diagram for. In the figure, 11 _{1 to} 11 _n are flip-flops, 30 is an AND function, and 31 is an OR function.

Claims (3)

[Claims] 1. A test method for a shift register comprising n (n is an integer of 2 or more) flip-flops (11 ^{1 to} 11 _n ) connected in cascade, wherein the shift register has a logical value "1" or "1". At least (n-1) continuous burst data of "0" are shift-input, test data whose logical value is inverted with respect to the burst data are shift-input, and the setting data of the shift register is (n-1) A test method for a shift register, which comprises shifting and detecting a failure depending on whether or not the test data is output from the shift register. 2. A shift register test method comprising n (n is an integer of 2 or more) flip-flops (11 ^{1 to} 11 _n ) connected in cascade, wherein the n flip-flops have a logical value "1". To "preset" or clear to a logical value "0", shift input test data whose logical value is inverted with respect to the preset or clear, shift setting data of the shift register (n-1), and shift A test method for a shift register, wherein a failure is detected depending on whether or not the test data is output from the register. 3. A test method for a shift register comprising n (n is an integer of 2 or more) flip-flops (11 ^{1 to} 11 _n ) connected in cascade, wherein the shift register has a logical value "1" or "1". The test data of 0 "is shift-input, the logical value is inverted with respect to the test data, and at least (n-1) continuous burst data is shift-input, and the output of the test data from the shift register is performed. A method for testing a shift register, which is characterized by detecting a failure by means of a method.