JPH0599987A - Test circuit - Google Patents

Abstract

PURPOSE:To eliminate the burden on the design of a test circuit caused when the validity of the delay time of the test circuit is not known by comparing a signal output from a large-scale functional block and an output expecting value signal and detecting the agreement/disagreement therebetween. CONSTITUTION:(n) signals 104 are output from a large-scale functional block 2 corresponding to (m) signals 101 input through an input terminal 51. The (n) signals 104 are input to a test circuit 1. On the other hand, a mode switching signal 103 is input to the circuit 1 to switch the circuit 1 to either of a comparing function and an output signal selecting function. When the signal 103 is set at the H level and the comparing function is selected, (n) output expecting value signals 102 are compared with the signals 104 in the circuit 1, and a signal 105 resulting from the comparison is output. If the signal 103 is set at the L level to select the output signal selecting function, the signal 104 is selected via the signal 102 and output from the circuit 1 as a signal 105 of the selecting result.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a test circuit, and more particularly to a test circuit used for testing a large scale functional block in a semiconductor integrated circuit.

[0002]

2. Description of the Related Art In a conventional test circuit of this type, as shown in FIG. 3, in order to avoid malfunction due to fluctuations in internal power supply potential and ground potential caused by simultaneous operation of output signals in a semiconductor integrated circuit. , A part of the output of the large-scale functional block 11 is output to the semiconductor integrated circuit via the delay circuits 12, 13 and 14 each having a different delay amount for each output group within the allowable range of the number of simultaneous output operations. Tested as output signal or Figure 4
As shown in, the comparison circuit 16 compares the output signal of the large-scale functional block 15 with the external input signal input from the terminal 64, and outputs the comparison result from the terminal 65 as a comparison result signal for testing. It is generally done.

[0003]

In the conventional test circuit described above, in the case of the test circuit shown in FIG. 3, the larger the number of output signals of the large-scale functional block, the further,
The larger the number of large-scale functional blocks tested in parallel, the larger the number of delay circuits. In addition, it is necessary to investigate the delay time of each output signal of the large-scale functional block in advance and adjust the delay time of the test circuit.The delay time of the test circuit must be adjusted until the number of simultaneous output operations is confirmed by simulation. Since the validity is unclear, there is a drawback that the burden on the circuit design increases.

Further, in the case of the test circuit of FIG. 4, the comparison result signal output from the comparison circuit only provides information on the match / mismatch between the output signal of the large-scale functional block and the external input signal. However, there is a drawback in that it is not possible to check the cause of the mismatch when they do not match.

[0005]

The test circuit of the present invention comprises:
In a semiconductor integrated circuit having at least one large-scale functional block, an output signal of the large-scale functional block and a predetermined output expected value signal input from the outside are compared and collated in a 1-bit section, and both of the signals are compared. A function of outputting a comparison result signal for identifying a match / mismatch, and an output signal of the large-scale functional block is arbitrarily selected via the output expected value signal, and the selected output signal is output as a selection result signal. And a signal comparison / selection circuit that operates by selecting one of the functions via a predetermined test mode switching signal.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1A shows a test circuit 1 according to a first embodiment of the present invention and a large-scale functional block 2 to be tested.
2 is a block diagram showing a correspondence relationship with FIG.
FIG. 7B is a circuit diagram showing the test circuit of this embodiment. As shown in FIG. 1B, in the present embodiment, signal comparison / selection circuits 3-1, 3-2, ..., 3-n (including NAND circuits 4 and 7 and OR circuits 5 and 6) are provided. n
Is a positive integer) and these n signal comparison / selection circuits 3-
, 3-2, ..., 3-n AND-input AND circuit 8 that takes the logical product of the output signals. The internal configuration of the signal comparison / selection circuits 3-2 to 3-n is exactly the same as that of the signal comparison / selection circuit 3-1.
The description is omitted.

1A and 1B, n signals 104 are output from the large-scale functional block 2 corresponding to the m signals 101 input from the input terminal 51, and the test circuit 1 Entered in. On the other hand, the mode switching signal 103 is input to the test circuit 1 from the input terminal 53, and the function of the test circuit 1 is switched to either the comparison function or the output signal selection function. When the mode switching signal 103 is set to the “H” level and the comparison function is selected,
Large-scale functional block 2 input from external input terminal 52
N output expected value signals 102 of the signal 104 output from the large-scale functional block 2 in the test circuit 1.
The comparison result signal 105 is compared and collated with the output terminal 5
4 is output.

When the mode switching signal 103 is set to "L" level and the output signal selection function is selected, the signal 104 output from the large-scale functional block 2 is selected.
Is selected via the output expected value signal 102 of the large-scale functional block 2 input from the external input terminal 52, and the output terminal 54 is selected as the selection result signal 105 by the test circuit 1.
Is output via.

In FIG. 1B, the mode switching signal 10
3 is set to the "H" level and the comparison function is selected, the signal comparison / selection circuit 3-1 in the test circuit 1 outputs the signal 104 output from the large-scale functional block 2 to the NAND circuit. 4 and the OR circuit 5, the expected output value signal 102 is input to the NAND circuit 4, the OR circuits 5 and 6, and the “H” level mode switching signal 103 is input to the OR circuit 6. The outputs of these NAND circuit 4, OR circuits 5 and 6 are N
It is input to the AND circuit 7, and then input to the AND circuit 8 as the output of the signal comparison / selection circuit 3-1. In this case, when the signal 104 input from the large-scale functional block 2 matches the output expected value signal 102 input from the external input terminal 52, the signal comparison / selection circuit 3-1 outputs the “H” level. Further, if they do not match, the "L" level is output. This operation is exactly the same for the other signal comparison / selection circuits 3-2 to 3-n, and is "H" in response to the match or mismatch of both signals for each 1 bit.
A level or “L” level signal is output and input to the AND circuit 8. Therefore, when the signals output from all the signal comparison / selection circuits 3-1, 3-2, ..., 3-n are "H" level, the selection result signal output from the AND circuit 8 The "H" level is output as 105, which indicates that the comparison results are in agreement. Further, when at least one of the signal comparison / selection circuits corresponding to 1 bit has a mismatched state, the level of the comparison result signal 105 output from the output terminal 54 becomes “L” level, It is shown that the comparison results do not match.

In the mode corresponding to the output signal selection function, the mode switching signal 103 is set to the "L" level and the signal comparison / selection circuit 3 corresponding to each 1 bit.
-1, 3-2, ..., 3-n are respectively used as selectors. In this case, as a selection signal from the external input terminal 52, any one bit out of n bits is set to the “H” level, and the other bits are set to the “L” level to be input from the large-scale functional block 2. The signal of the corresponding bit is selected from the n-bit signals and output from the output terminal 54.

Next, FIG. 2A is a block diagram showing the correspondence between the test circuit 1 of the second embodiment of the present invention and the large-scale functional block 2 to be tested, and FIG. 2 (b) is a circuit diagram showing the test circuit of this embodiment. As shown in FIG. 2B, in this embodiment, signal comparison / selection circuits 3-1, 3-2, ..., 3-n including NAND circuits 4, 7 and OR circuits 5, 6 are provided. ,
These n signal comparison / selection circuits 3-1, 3-2, ...
......, AND of n inputs that takes the logical product of the output signals of 3-n
A j-input AND circuit that ANDs the output signals of the circuit 8 and j (j is a positive integer: j <n) signal comparison / selection circuits 3-1, 3-2, ... 9 and (n−j) signal comparison / selection circuits 3- (j + 1), 3- (j + 2), ...
.., and an AND circuit 10 having (n-j) inputs that take the logical product of the output signals of 3-n. The internal configuration of each signal comparison / selection circuit other than the signal comparison / selection circuit 3-1 is exactly the same as that of the signal comparison / selection circuit 3-1, and thus the description thereof is omitted.

In this embodiment, by adding AND circuits 9 and 10 in addition to the AND circuit 8, the comparison result signal 110 in the comparison function mode is output terminal 58.
In the output signal selection function mode, the selection result signals 111 and 112 are output.
It is configured to output from 0. In this way, by outputting the selection result signals in parallel, it is possible to select and examine the output signal from the large-scale functional block 2 in a shorter time than the output signal selection function in the first embodiment. Become.

[0014]

As described above, according to the present invention, it is possible to compare the signal output from the large-scale functional block with the output expected value signal in 1-bit sections and detect the match / mismatch. , The use of delay circuit is unnecessary, and the burden on the circuit design due to the uncertain validity of the delay time of the test circuit can be eliminated, and the malfunction in the large-scale functional block is caused through the signal selection function. There is an effect that a signal to be processed can be easily selected and examined.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a block diagram showing a second embodiment of the present invention.

FIG. 3 is a block diagram showing a conventional example.

FIG. 4 is a block diagram showing another conventional example.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 test circuit 2, 11, 15 large-scale functional block 3-1 to 3-n signal comparison / selection circuit 4, 7 NAND circuit 5, 6 OR circuit 8-10 AND circuit 12-14 delay circuit 16 comparison circuit

Claims (1)

[Claims] 1. In a semiconductor integrated circuit having at least one large-scale functional block, an output signal of the large-scale functional block and a predetermined output expected value signal input from the outside are compared and collated in a 1-bit section. , A function of outputting a comparison result signal for identifying a match / mismatch between the two signals, and an output signal of the large-scale functional block is arbitrarily selected via the output expected value signal, and the selected output signal is It also has the function of outputting as a selection result signal,
A test circuit comprising a signal comparison / selection circuit which operates by selecting one of the functions via a predetermined test mode switching signal.