JP2613674B2 - Integrated circuit device - Google Patents

Description

The present invention relates to an integrated circuit device having a built-in memory.

[Prior Art] A conventional integrated circuit device in which a system including a CPU (central processing unit), a peripheral circuit, a ROM (read only memory), and the like is formed on one semiconductor chip is used to determine the quality of the ROM. ROM mode by setting the test mode
The data written in the ROM can be read out to the outside, and the quality of the ROM is determined by comparing the read data with predetermined data.

[Problems to be Solved by the Invention] However, in the above-mentioned conventional integrated circuit device, anyone can easily obtain the data in the ROM, and therefore cannot keep the data in the ROM secret. There's a problem.

The present invention has been made in view of the above problems, and without reading out data stored in a memory to the outside,
An object of the present invention is to provide an integrated circuit device capable of determining the quality of the memory.

[Means for Solving the Problems] An object of the present invention is to provide an integrated circuit device including a memory and a data input / output circuit, in which data is input from the outside to the data input / output circuit to determine the quality of the memory. Means for setting a test mode that can only perform the test mode, means for sequentially comparing data supplied from the outside when the test mode is set and data read from the memory, and means for externally supplied data and memory read data. Output control means for outputting a match detection signal when all the comparison results match, and outputting a mismatch detection signal when there is one or more mismatches, and means for outputting the output of the output control means to the outside And the output control means is a counter that counts the coincidence detection signal.

[Operation] When determining whether data written in a memory such as a ROM built in an integrated circuit device is normal, first, a test mode is set. As a result, the data input / output circuit is prohibited from outputting data, and enters a state in which it can only input data. In this state, predetermined data is externally input to the integrated circuit device. The integrated circuit device compares the input data with the data read from the memory, and outputs a signal indicating whether or not they match to the outside. Thus, the quality of the memory can be determined without deteriorating the confidentiality of the memory.

Embodiment An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a main block diagram showing an embodiment of an integrated circuit device according to the present invention, FIG. 2 is a circuit diagram showing a specific example of a comparison circuit shown in FIG. 1, and FIG. FIG. 4 is a circuit diagram illustrating a specific example of a unit.

The integrated circuit device of FIG. 1 includes a CPU (not shown), a peripheral circuit and a memory associated with the CPU.

In FIG. 1, reference numeral 11 denotes a ROM, and reference numeral 12 denotes a data input / output unit for inputting / outputting data to / from the outside. The data input / output unit is connected to a data input / output terminal 14 via a data bus 13. A comparison circuit 16 compares the data D _EXT input from the outside via the data input / output unit 12 and the internal data bus 15a with a data D _ROM read from the ROM 11 via the internal data bus 15b.
A control circuit that sets the data input / output 12 to a state where only input can be performed and activates the comparison circuit 16 when testing the M11. An output control unit 18 outputs the comparison result only once at a predetermined timing. It is.

Further, the integrated circuit device has an input terminal 19 for inputting an address signal a for specifying an address of the ROM 11,
An input terminal 20 for inputting a ROM selection signal b for activating M11, an input terminal 21 for inputting a ROM data output signal c for instructing the ROM 11 to read data, and a comparison output from the output control unit 18. An output terminal 22 for extracting the result signal d to the outside is provided.

Next, a specific configuration example of the comparison circuit 16 in FIG. 1 will be described with reference to FIG. 2 and FIG. Comparator circuit of FIG. 2 is for comparing the 8-bit data D _ROM read from the 8-bit data D _EXT and ROM11 from outside for each bit, each bit (D1 to D7 ) Are provided with eight bit comparison circuits 23 corresponding one-to-one.

Each bit comparison circuit 23 includes an AND gate G1, a NOR gate G2, and an OR gate G3 connected to outputs of these gates. For example, when the first bit D0 of the data D _EXT and the first bit D0 of the data D _ROM are equal to each other, "1" is output from the OR gate G3 of the uppermost bit comparison circuit 23 in FIG. “0” is output.

The output of each bit comparison circuit is connected to the input of a NAND gate G4, and the output of the NAND gate G4 is 1 byte, that is,
This becomes a 1-byte comparison result signal e indicating the result of the comparison for D0 to D7. When the data D _EXT matches the data D _ROM for all of D0 to D7, the inputs of the AND gate G4 are all "1", and the 1-byte comparison result signal is "0".

Next, a specific configuration example of the output control unit 18 in FIG. 1 will be described with reference to FIG. The output control section 18 includes 13 stages of D flip-flops F1, F2,..., F13 connected in series, and has a circuit configuration corresponding to a ROM capacity of 8 Kbytes. Flip-flop F1, F2, ... F13 is 1 byte comparison result output from the comparator circuit 23 when the 1-byte data of the data D _EXT and read from the ROM11 data D _ROM from the outside matches This is a counter that counts up the number of signals. When data match for all 8 Kbytes, "1" is supplied to one input of the AND gate 24 from the last flip-flop F13.

The other input of AND gate 24 is connected to R via inverter 25.
Since the signal ROMTST set to “0” is supplied when testing the OM11, the comparison result signal d is output only in the test mode.

Next, the operation of the integrated circuit device having the above configuration will be described.

When the test mode is selected, the control circuit 17 sets the data input / output circuit 12 to a state where only input can be performed, activates the comparison circuit 16, and further sets the signal ROMTST to "0". Address signal a from the outside in this state, ROM selection signal b, sequentially read out the data D _ROM to ROM data output signal c is stored in the ROM11 when supplied to the ROM11 through the respective input terminals 19, 20 and 21 The data D _EXT is input to the comparison circuit 16 and sequentially input to the comparison circuit 16 via the data input / output terminal 14 from the outside.

When these 1-byte data match, the comparison circuit 16 supplies "0" to the output control unit 18 as a 1-byte comparison result signal e. D _ROM and D _EXT for all 8K bytes
If There they match, the output control circuit 18 and second ¹³ "0"
, And a comparison result signal d indicating that the ROM 11 is normal is output from the output terminal 22 to the outside through the AND gater 24 from the last-stage flip-flop F13.

In the above embodiment, the capacity of the ROM 11 is 8 Kbytes. However, by changing the number of flip-flops of the output control unit 18, it is possible to support an arbitrary ROM capacity such as 2 Kbytes, 4 Kbytes, 16 Kbytes, and 32 Kbytes. be able to.

[Effects of the Invention] The integrated circuit device of the present invention sets the data input / output unit to a state in which only input is possible when the test mode is set to determine the quality of the built-in memory, and receives an external input. And the data read from the memory are compared inside the integrated circuit device, and the comparison result is output to the outside by a signal different from the data in the memory. Data can be kept confidential.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the integrated circuit device of the present invention, FIG. 2 is a circuit diagram of the comparison circuit of FIG. 1, and FIG. 3 is a circuit diagram of the output control unit of FIG. . 11 ROM: 12 Data input / output unit 16 Comparison circuit 1
7 ... Control circuit, 18 ... Output control unit, G1 ... AND gate,
G2: NOR gate, G3: OR gate, F1 to F3: flip-flop.

Claims (1)

(57) [Claims] 1. An integrated circuit device including a memory and a data input / output circuit, wherein the data input / output circuit is set to a test mode in which only data can be externally input in order to judge the quality of the memory. Means for sequentially comparing data supplied from the outside when the test mode is set with data read from the memory, wherein each comparison result between the externally supplied data and the memory read data is An output control unit that outputs a match detection signal when all match, and outputs a mismatch detection signal when there is one or more mismatches, and a unit that outputs an output of the output control unit to the outside; The integrated circuit device, wherein the output control means is a counter that counts a coincidence detection signal.