JPH0582905B2 - - Google Patents

Description

[Detailed Description of the Invention] [Technical Field of the Invention] This invention relates to a test circuit for a semiconductor integrated circuit,
In particular, the present invention relates to an improvement in which an arbitrary number of test mode signals can be generated based on signals input from a limited number of external terminals.

[Technical Background of the Invention] Generally, a semiconductor integrated circuit is constructed by integrating several thousand to tens of thousands of transistors on a semiconductor chip several millimeters square, and this chip is housed in a package made of plastic, ceramic, etc. to produce a product. .
Therefore, when checking the operating status of the chip after storing it in the package or inputting/outputting signals for operation control, the external Limited to terminals (pins) only. Therefore, when designing a semiconductor integrated circuit, it is common to incorporate a test circuit that can arbitrarily set the internal state of the chip from the outside for chip verification. When this test circuit is built-in, it is usually necessary to provide external terminals for setting test modes as many times as there are test modes. However, since the number of external terminals of an integrated circuit is limited for each package, it is desirable to have as few external terminals as possible for testing. Conventionally, methods such as providing a special counter inside the chip have been considered in order to minimize the number of external terminals dedicated to the test circuit.

FIG. 4 is a circuit diagram showing the configuration of a conventional test circuit. 1, ... are T-type flip-flops, and n flip-flops 1 are connected in multiple stages such that the Q output of the previous stage is the T input of the next stage.
The total constitutes an n-bit pinariap counter 2. The pulse signal φ supplied to the external terminal 3 as a T input is input to the flip-flop 1 at the first stage, and the reset signal RST supplied to the external terminal 4 as a reset input is input in parallel to all the flip-flops 1. The n NOR gates ₅₁ to _5o are used for decoding, into which arbitrary signals among the Q outputs and outputs of the n flip-flops 1 are input in parallel, and output test mode signals M1 to Mn from these signals. For example, one NOR gate ₅₁ has the Q outputs of all flip-flops 1 inputted in parallel, and one NOR gate ₅₂ has the outputs of the first stage flip-flop 1 and the Q outputs of each flip-flop 1 from the second stage onwards. Outputs are input in parallel. Therefore, the n Noah gates 5 ₁ to 5 _o
In this case, 2 ⁿ test mode signals can be obtained.

FIG. 5 is a timing chart showing the operation of the conventional circuit. First, send a reset signal to terminal 4.
After supplying RST, a predetermined number of pulse signals φ are supplied to terminal 3. As a result, up counter 2
The Q outputs Q(1) to Q(n) of the flip-flops 1 in each stage change binary depending on the number of inputs of the pulse signal φ. In response to these signal changes, decoded mode signals M1 to Mn are sequentially output from the NOR gates ₅₁ to _5o .

In an integrated circuit with such a built-in test circuit, a test mode is set internally according to each of the above test mode signals M1 to Mn, and a functional test,
Circuit settings are made for various verification tests such as DC tests.

[Problems with Background Art] As described above, an integrated circuit is housed in a package with a limited number of pins, and the smaller the number of pins, the smaller the external appearance of the package and the lower the manufacturing cost. For this reason, it is desirable for an integrated circuit to have as few external terminals as possible. However, in addition to the original external terminal, the conventional test circuit requires two additional terminals for supplying the pulse signal φ and the reset signal RST to the test circuit. These two terminals are completely unused and useless when the integrated circuit is actually used.

[Object of the Invention] This invention was made in consideration of the above circumstances, and its purpose is to reduce the number of external terminals required for testing compared to the conventional one, and to enable arbitrary test modes. The objective is to provide a test circuit that can be freely set from the outside.

[Summary of the invention] In order to achieve the above object, this invention has the following features:
an external terminal to which a predetermined pattern consisting of multiple bits of data is supplied, a data shift circuit in which an arbitrary number of data shift means are connected in multiple stages and the pattern is inputted to the first stage data shift means, and the plurality of data at least one first gate circuit for detecting a specific output state of the shifting means; a latch circuit for latching the output of the first gate circuit; A second gate circuit generates a reset signal for resetting the circuit, and the output of the latch circuit is used as a test mode signal.

[Embodiment of the Invention] An embodiment of the invention will be described below with reference to the drawings.

FIG. 1 is a circuit diagram showing the configuration of a test circuit according to the present invention, and this test circuit is built in an integrated circuit to be verified as in the conventional case. In the figure, 11 to 14 are shift registers, and these four shift registers are connected in multiple stages such that the Q output of the previous stage is used as the D input of the next stage, and constitute a 4-bit data shift circuit 15 as a whole. . Pattern data is supplied to the external terminal 16 as a D input to the first stage shift register 11.
Din is input, and the basic clock signal φ used in the integrated circuit in which this test circuit is built is supplied in parallel to the clock input terminals of all shift registers 11 to 14.

17 and 18 are AND gates with 3 inputs each,
19 is a 3-input NAND gate, the AND gate 17 is supplied with the Q output of the shift register 12 and each output of the shift registers 13 and 14, and the AND gate 18 is supplied with the Q output of the shift register 12, 13 and shift register 14
The NAND gate 19 is supplied with the Q outputs of the shift registers 12, 13 and 14.

The two shift registers 20 and 21 are for generating two types of test mode signals M1 and M2.
The outputs of the AND gates 17 and 18 are supplied as inputs. Furthermore, both shift registers 2
The output of the NAND gate 19 is supplied as a reset input of 0 and 21. Two types of test mode signals M1 and M2 are obtained as respective Q outputs.

Another shift register 22 is for generating a clock signal for controlling the data latch operation in both shift registers 20 and 21, and this shift register 22 has a D input as a clock signal for the first stage shift in the data shift circuit 15. The output of register 11 is supplied, and the signal φ is supplied via inverter 23 as a clock signal. The Q output of this shift register 22 serves as a clock signal for the shift registers 20 and 21.
is supplied to

Next, the operation of the circuit configured as described above will be explained using timing charts shown in FIGS. 2 and 3.

First, as pattern data Din, as shown in FIG. 2, the clock signal φ, which is set to "1" during a 3-bit period, is sequentially inputted from the external terminal 16. This pattern data Din is sequentially shifted one bit at a time by the data shift circuit 15 in synchronization with the clock signal φ.
5 shift registers 11 to 1
As shown in FIG. 2, each of the four Q outputs Q1 to Q4 has a "1" period shifted by one bit. And each Q output of shift registers 11 to 14
When Q1 to Q4 are all set to "1", the output N of the NAND gate 19 becomes "0" for the first time, which resets the shift registers 20 and 21 and both test mode signals M1 and M2 are set to "0". Ru.

Next, after inputting “0” for arbitrary bits as pattern data Din, “0”, “0”, “1”, “0”
A 4-bit pattern consisting of The pattern data at this time is also sequentially shifted bit by bit by the data shift circuit 15 as in the above case, so each of the Q outputs Q1 to Q4 of the four shift registers 11 to 14 constituting the data shift circuit 15 is The state is shifted by one bit.

On the other hand, the shift register 22 operates the data shift circuit 15 in synchronization with an inverted signal of the clock signal φ, that is, a signal shifted by half a bit with respect to the clock signal φ.
In order to take the output of the first stage shift register 11 inside, the Q output of this shift register 22 is
Q22 inputs the 4-bit pattern as described above, shifts the 4-bit pattern to the shift register 14 at the final stage, and then rises from "0" to "1". Moreover, this Q output Q22 rises to "1" in the middle of the change point of the clock signal φ. When the Q output Q22 of the shift register 22 rises to "1", the Q output Q2 of the shift register 12 input to the AND gate 17, the output 3 of the shift register 13, and the shift register 14
The outputs 4 of both are set to "1", and the output of the AND gate 17 is also set to "1". Therefore, when the Q output Q22 of the shift register 22 rises to "1", the "1" output of the AND gate 17 is taken into the shift register 20, and after that,
Test mode signal M1 is set to "1". Therefore, the test mode signal M1 set to "1" in this way
By setting the test mode internally using , it is possible to perform circuit settings for various verification tests such as functional tests and DC tests in the same way as in the past.

FIG. 3 is a timing chart showing different operations of the above embodiment circuit. In this case, after resetting the shift registers 20 and 21 in the same manner as above, a 4-bit pattern consisting of "0", "1", "1", "0" is sent to the external terminal as pattern data Din. Inputs are made sequentially from 16 onwards. In this case, when the Q output Q22 of the shift register 22 rises from “0” to “1”,
The Q output Q2 of the shift register 12, the Q output Q3 of the shift register 13, and the output 4 of the shift register 14, which are input to the AND gate 18, are all set to "1".
The output of is set to "1". Therefore, when the Q output Q22 of the shift register 22 rises to "1", the "1" output of the AND gate 18 is taken into the shift register 21, and thereafter the test mode signal M2 is set to "1". Therefore, in this case, circuit settings are performed for various verification tests such as a functional test and a DC test using the test mode signal M2.

In this way, in the above embodiment circuit, only one external terminal 16 is provided for the test circuit, and this terminal 1
Since two types of test mode signals M1 and M2 are generated by inputting predetermined pattern data Din to 6, the number of external terminals is reduced to one compared to the two required in the conventional circuit. can. In addition, by increasing the number of shift registers connected in the data shift circuit 15, the types of test mode signals can be increased, which allows any test mode to be freely controlled from the outside using only one external terminal. Can be set.

[Effects of the Invention] As explained above, according to the present invention, the number of external terminals required for testing can be reduced compared to the conventional test, and any test mode can be freely set from the outside. The circuit can be provided.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing the configuration of a test circuit according to the present invention, FIGS. 2 and 3 are timing charts showing the operation of the above embodiment circuit, and FIG.
The figure is a circuit diagram of a conventional circuit, and FIG. 5 is a timing chart showing the operation of the conventional circuit. 11, 12, 13, 14, 20, 21, 22...
...Shift register, 15...Data shift circuit,
16...External terminal, 17, 18...AND gate, 19...NAND gate, 23...Inverter.

Claims (1)

[Claims] 1. A data shifter in which an external terminal to which a predetermined pattern consisting of data of multiple bits is supplied and an arbitrary number of data shift means are connected in multiple stages, and the pattern is input to the data shift means in the first stage. a circuit, at least one first gate circuit for detecting a specific output state of the plurality of data shifting means, a latch circuit for latching the output of the first gate circuit, and a specific pattern supplied to the external terminal. a second gate circuit that generates a reset signal for resetting the latch circuit by detecting the latch circuit, and the output of the latch circuit is used as a test mode signal. 2. The test circuit according to claim 1, wherein said latch circuit is controlled by a latch control signal generated by a latch control signal generating means based on a clock signal and a pattern supplied to said external terminal.