JP2901828B2 - Semiconductor integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit including a central processing circuit and a storage circuit, and including circuits necessary for functional testing of these circuits.

[0002]

2. Description of the Related Art Generally, before a semiconductor integrated circuit is shipped as a product, various functional tests are performed to confirm whether the functions described in specifications are satisfied.

FIG. 5 is a block diagram showing an electrical configuration of a conventional semiconductor integrated circuit 1 and a test apparatus 2 for performing a function test thereof. The semiconductor integrated circuit 1 includes a central processing unit (hereinafter abbreviated as “CPU”) 3, a read-only memory (hereinafter abbreviated as “ROM”) 4, and the like, and a method for testing its function will be described below.

The function test of the CPU 2 includes a CPU function test using an external instruction signal (hereinafter, abbreviated as “external instruction test”). When performing this test, first, an external instruction signal, that is, an instruction code is supplied from the test input circuit 6 to the CPU 3 through the external instruction input terminals TI1 to TIn (the reference numeral 7 is used when collectively referred to). The test input circuit 6 supplies an instruction code in synchronization with an instruction cycle of the CPU 3 (a unit cycle for performing processing based on the instruction code).
Clock signal φ1 and clock signal φ2 are input from a clock output terminal for synchronization.

Next, when an instruction code is given to the CPU 3, an output value corresponding to the instruction code is given from the CPU 3 to the comparison circuit 11 via the data bus 9b. Random access memory (hereinafter abbreviated as “RAM”) 12
Stores, in advance, output values corresponding to a plurality of instruction codes as expected values, and the expected value corresponding to the
3 and output to the comparison circuit 11. Therefore, the comparison circuit 11 latches the expected value in advance, compares it with the output value output from the CPU 3, determines whether or not both values match, and outputs the determination result to the CPU determination signal. Test device 2 via output terminal 19
Output to In this way, the test apparatus 2 repeats the above-described external instruction test for a plurality of predetermined instruction codes, and based on the determination result,
Function is determined.

[0006] In addition, a ROM-D
UMP test and so on. When performing this test, the counter 15 sequentially increments the count value in each cycle of the instruction cycle in synchronization with the clock signal φ2 output from the oscillation circuit 8, and uses the count value as an address signal in order to connect the address bus 10a to the address bus 10a. ROM through
Give to 4.

Next, when the address signal is applied to the ROM 4, the output value corresponding to the address signal is output to the test apparatus 2 via the data bus 9c and the output terminals TRD1 to TRDn (the reference numeral 16 is used when collectively referred to). Comparison circuit 17
Output to The comparison circuit 17 stores an expected value corresponding to the output value of the ROM 4 in advance, compares the output value of the ROM 4 with the expected value, and determines whether or not both values match. Do. In this manner, the test apparatus 2 stores the address in the predetermined range in the ROM
-The DUMP test is repeated, and R
The function of OM4 is determined.

As described above, the external instruction test of the CPU 3 and the DUMP test of the ROM 4 are simultaneously performed within the same instruction cycle.

FIG. 6 is a diagram showing details of the external instruction input terminal 7 and the ROM output terminal 16 shown in FIG. The external instruction input terminal 7 and the ROM output terminal 16 have n terminals TI1 to T1, respectively.
In and terminals TRD1 to TRDn.

FIG. 7 shows the external instruction signals I1-In and the ROM output data RD1-RD shown in FIG.
FIG. 3 is a circuit diagram of test terminals T1 to Tn that can input and output both n and n. When the test terminals are also used in this way, the number of test terminals shown in FIG. 7 can be reduced to half of the number of test terminals shown in FIG.

FIG. 8 shows test terminals T1 to T1 shown in FIG.
6 is a time chart when Tn is applied to the semiconductor integrated circuit 1 shown in FIG. 5 and a function test is performed. In this case, since the input terminal of the external instruction signal is also used as the output terminal of the ROM output data signal, the CPU function test by the external instruction signal and the ROM function test by the ROM output data cannot be performed at the same time. Therefore, the external instruction signal and the ROM output data are alternately input and output at each of the test cycles (two periods of the original clock X1) synchronized with the clock signal φ2 at the test terminals T1 to Tn. The ROM-DUMP test is performed alternately.

[0012]

In the conventional semiconductor integrated circuit, when the external instruction test using the external instruction signal and the ROM-DUMP test using the output data of the ROM are simultaneously performed as described above, the tests are performed alternately. As compared with the case, the number of input / output terminals for the test is greatly increased. Therefore, the manufacturing cost of the semiconductor integrated circuit increases.

Further, if the external instruction test and the ROM-DUMP test are alternately performed by using the input / output terminals alternately in order to reduce the number of test input / output terminals, the test time is greatly increased.

An object of the present invention is to quickly perform a function test of a built-in central processing circuit and a storage circuit,
Another object of the present invention is to provide a semiconductor integrated circuit having a low manufacturing cost.

[0015]

According to the present invention, there is provided a central processing circuit for executing an operation at a predetermined cycle based on an instruction code given from an external test apparatus, and a data read-out at a predetermined cycle. A first comparison circuit that compares the arithmetic processing result output from the central processing circuit with data stored in advance at the time of the function test, A second comparison circuit that compares data read from the storage circuit with expected value data given from the external test device to determine whether or not it is appropriate; In the cycle, the instruction code and the expected value data are alternately given, and the instruction code is held for the predetermined period and given to the central processing unit, and the expected value data is set in the predetermined value. A semiconductor integrated circuit which comprises an input circuit providing a second comparator circuit to hold between phases.

[0016]

As described above, according to the present invention, the central processing unit executes an operation at a predetermined cycle based on an instruction code given from an external test apparatus, and the storage circuit operates at the predetermined cycle. Data reading is performed. When performing a functional test, the first comparison circuit compares the operation processing result output from the central processing circuit with data stored in advance to determine whether or not it is appropriate. Appropriateness is determined by comparing data read from the storage with expected value data provided from an external test apparatus. At this time, the instruction code and the expected value data are input to the input circuit at a cycle shorter than the predetermined cycle from an external test apparatus.
Given alternately. The input circuit holds the instruction code for the predetermined period and supplies it to the central processing unit, and holds the expected value data for the predetermined period and supplies it to the second comparison circuit. Therefore, the function test of the central processing circuit and the function test of the storage circuit can be performed by simultaneously inputting a signal using the same input terminal and performing the function test simultaneously, and the number of input terminals does not increase.

Further, by providing the second comparison circuit, the signal to be output from the second comparison circuit to the outside only needs to be the signal of the determination result, so that the number of output terminals can be greatly reduced.

[0018]

FIG. 1 is a block diagram showing an electrical configuration of a semiconductor integrated circuit 31 according to an embodiment of the present invention and a test apparatus 32 for performing a function test thereof. Semiconductor integrated circuit 31
Is a central processing unit (hereinafter abbreviated as “CPU”) 3
3. Read-only memory (hereinafter abbreviated as “ROM”) 3
4 and the like, and the function test will be described below.

The function test of the CPU 32 includes a CPU function test using an external instruction signal (hereinafter, abbreviated as "external instruction test") and the like.
The 34 functional tests include a ROM-DUMP test and the like.
In this embodiment, the above-described external instruction test and ROM-DUMP test are simultaneously performed based on the time chart shown in FIG.

From the test input device 36 of the test device 32,
When the external test input signal A is applied to the test terminals TP1 to TPn
(The reference numeral 37 is used when collectively referred to).
In the external test input signal A, as shown in FIG. 2, the external instruction input signal B and the ROM expected value input signal C are combined in a time-division manner in each half cycle. An external instruction signal A1 is output at time t3 in synchronization with the rising of the clock signal φ2 at every instruction cycle (a unit time at which the CPU or the like performs processing based on the instruction code), and in synchronization with the rising of the clock signal φ1. At time t4, ROM expected value input signal A2 is output. The clock signal φ1 and the clock signal φ2 are generated based on the original clock signal X and output from the oscillation circuit 38. Clock signals φ1 and φ2 are output from the oscillation circuit 38 to the test input circuit 36, and the test input circuit 36
An external test input signal A is generated based on 1, φ2.

As shown in FIG. 3, the test / shared terminal TP1
To TPn can be input / output by using both the external test input signal A and the normal input / output signal P. Since the instruction code of the external instruction signal and the data of the ROM expected value input signal are composed of n bits, the number of the test / shared terminals 37 to which the signal is input / output is n.

The external instruction signal A1 included in the test input signal A input to the test / shared terminals TP1 to TPn is latched by the clock signal φ2 in the latch circuit 51, and the external instruction input signal B
Is generated. In addition, RO included in test input signal A
The M expected value input signal A2 is latched by the clock signal φ1 in the latch circuit 52, and the ROM expected value input signal C is generated. This external instruction signal B
And the ROM expected value input signal C, as shown in FIG.
It is output in each cycle t1 of the instruction cycle in synchronization with the clock signal φ2 and the clock signal φ1.

Next, the external instruction signal B is
The instruction code is input to the CPU 33 via the data bus 39a, that is, an instruction code is given to the CPU 33. CPU33
, An output value corresponding to the instruction code is supplied to the comparison circuit 41 via the data bus 39b. The random access memory (hereinafter abbreviated as “RAM”) 42 previously stores output values corresponding to a plurality of instruction codes as expected values, from which the corresponding expected values are read out by the CPU 33, and the comparison circuit 41 Is output to Therefore, the comparison circuit 41 latches the output expected value, compares the output value output from the CPU 33 with the output value, determines whether or not both values match, and determines the determination result by the CPU determination. The output signal is output to the test device 32 via the output terminal 46. Thus, the test apparatus 32 repeats the above-described external instruction test for a plurality of predetermined instruction codes, and determines the function of the CPU 33 based on the determination result.

Next, the ROM expected value input signal C is output to the comparison circuit 45. In addition, the counter 35 includes the oscillation circuit 3
8 is sequentially incremented in synchronization with the clock signal φ2 output from the ROM 8, and the count value is sequentially used as an address signal in the ROM 3 via the address bus 10a.
Give to 4. When an address signal is applied to ROM 34, internal ROM data D corresponding to the address signal is output to comparison circuit 45 via data bus 39c.
Therefore, the comparison circuit 45 outputs the ROM expected value input signal C
Is compared with the value of the internal ROM data D, it is determined whether or not both values match, and the determination result is output to the test apparatus 32 via the output terminal 47 as a ROM determination output signal. I do.

As described above, the test apparatus 2 repeats the above-described function test for the address in the predetermined range, and determines the function of the ROM 43 based on the determination result.

Although the expected ROM input signal C and the internal ROM data D have the same period (instruction cycle t1) as shown in FIG. 2, the phase of the expected ROM input signal is the same as that of the internal ROM data D. Time t3, that is, 1/1 of instruction cycle t1
Two cycles late. Therefore, the value of the expected ROM input signal C and the value of the internal ROM data D can be compared only at time t4 for each instruction cycle t1. Also, in the comparison circuit 45, the comparison circuit 45
As a result of comparing the data values in the above, if the data values match, the ROM determination output signal F is output at a high level; otherwise, the ROM determination output signal F is output at a low level. Also, the ROM test strobe signal G
Is output at a timing when the ROM determination output signal is stabilized. When the level of the determination circuit output signal F is determined in synchronization with the ROM data strobe signal G, the accurate comparison circuit 4
5 can be obtained.

FIG. 4 is an electric circuit diagram of the comparison circuit 45. The comparison circuit 45 includes the EX. It comprises NOR gates 61 to 6n and an AND gate 70. n EX. N
OR gates 61 to 6n are composed of an n-bit internal ROM.
The data D and the expected ROM input signal C are compared for each corresponding bit. When the values of the corresponding bits of the internal ROM data D and the ROM expected value input C are equal,
That is, when any of the signals is at the low level or the high level, the output E of the comparison circuit 45 is at the high level.

Therefore, the internal ROM data D and the ROM
If the values of all corresponding bits of the expected value input signal C are equal, the inputs of the AND gate 70 all go high, so that the output of the AND gate 70, that is, RO
The M determination output signal F becomes high level. Also, internal RO
If at least one corresponding bit value of the M data D and the ROM expected value input signal C is different, the output of the AND gate 70 becomes low level, so that the ROM determination output signal F becomes low level.

[0029]

As described above, according to the present invention, the expected value input of the storage circuit and the instruction code to the central processing unit are time-divisionally divided into the same input terminal with a period shorter than a predetermined period. By alternately inputting data and latching the data at predetermined intervals, the function tests of the storage circuit and the central processing circuit can be performed simultaneously. Therefore, the time required for the function test can be significantly reduced. Also, by using the terminal for inputting the expected value and the terminal for inputting the instruction code, the number of input terminals does not increase.

Further, in the function test of the storage circuit, a second comparison circuit for comparing the output value from the storage circuit with the expected value is provided inside, so that only the determination result can be output to the outside. The number of output terminals can be greatly reduced.

Therefore, by using the semiconductor integrated circuit of the present invention, the function test of the built-in central processing circuit and the storage circuit can be performed quickly, and the manufacturing cost of the semiconductor integrated circuit can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an electrical configuration of a semiconductor integrated circuit 31 according to an embodiment of the present invention and a test apparatus 2 for performing a function test thereof.

FIG. 2 is a time chart in a function test of the semiconductor integrated circuit 31 shown in FIG.

FIG. 3 is a circuit diagram of an input circuit including a test / use terminal 37 shown in FIG.

FIG. 4 is an electric circuit diagram of a comparison circuit 45 shown in FIG.

FIG. 5 is a block diagram showing an electrical configuration of a conventional semiconductor integrated circuit 1 and a test apparatus 2 for performing a function test thereof.

6 is a circuit diagram showing an external instruction input terminal 7 and a ROM output terminal 16 shown in FIG.

FIG. 7 is a circuit diagram of a conventional input circuit including test terminals T1 to Tn.

8 is a time chart in a function test of a conventional semiconductor integrated circuit including the test terminal of FIG. 7;

[Explanation of symbols]

 REFERENCE SIGNS LIST 31 semiconductor integrated circuit 32 test apparatus 33 CPU 34 ROM 35 counter 36 test input circuit 37 test / shared terminal 38 oscillation circuit 39 data bus 40 address bus 42 RAM 41, 45 comparison circuit

Claims (1)

(57) [Claims] 1. A central processing circuit for executing an operation at a predetermined cycle based on an instruction code given from an external test apparatus; a storage circuit for reading data at the predetermined cycle; A first comparison circuit that compares an arithmetic processing result output from the central processing circuit with data stored in advance and determines whether the data is appropriate, and a data read from the storage circuit during a functional test. When,
A second comparison circuit that compares the expected value data given from the external test device to determine whether or not the instruction code is correct; and a command code and expected value data that are shorter than the predetermined period from the external test device. Are given alternately,
An input circuit for holding an instruction code for the predetermined period and providing the instruction code to the central processing circuit, and holding expected value data for the predetermined period and providing the expected value data to a second comparison circuit. Integrated circuit.