JPH05258599A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To apply a stress equal to a conventional stress on a unit bit without prolonging a burn-in time through the stress applied on the unit bit is decreased as a memory capacity is increased. CONSTITUTION:When a burn-in mode setting signal BTM is set to high level, by two 2 input logical AND circuits 2 and 3 and a logical OR circuit 4 to input the outputs of the circuits 2 and 3 as two inputs, a frequency is doubled by taking an exclusive-OR between a normal operating memory access clock signal CLK1 and a clock signal CLK2 which is used to a memory access at the time of a burn-in operation in a conventional semiconductor storage device. And a circuit, which outputs the signal as memory access clock signal CLK3 at the time of a burn-in, is provided.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device.

[0002]

2. Description of the Related Art Burn-in for applying high temperature / high voltage stress to a product is carried out for the purpose of removing an initial defect as a screening in an IC manufacturing process and for a life test in a reliability test of an IC. There are two types of burn-in, static burn-in and dynamic burn-in. The subject of the present invention is dynamic burn-in in which the product is in an operating state.

When performing dynamic burn-in, one word of data is accessed using the clock of a certain fixed cycle input from the outside as it is. However, since the clock input from the outside is always used in a constant cycle regardless of the speedup of the memory, the access operation time of one word of data when the recent speeded up memory is actually used is used. On the other hand, the access operation time at the time of burn-in is about 10 times.

Moreover, since the burn-in execution time has not changed in spite of the increase in the capacity of the memory in recent years, the stress applied to a unit bit by the burn-in tends to be reduced as compared with the actual use state. ..

[0005]

In the burn-in in the conventional semiconductor memory device as described above, when the capacity of the memory is further increased, if the burn-in execution time is kept the same as the current state, the stress applied per unit bit is reduced. Therefore, the life test and screening effect in the reliability test cannot be expected. Moreover, in order to keep the stress applied per unit bit as it is,
There was a problem that the burn-in implementation time had to be extended.

[0006]

The semiconductor memory device of the present invention is characterized in that it has a circuit for judging whether or not it is in the burn-in mode and switching the frequency of the memory access clock.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, an optimum embodiment of the present invention will be described with reference to the drawings. FIG. 1A is a block diagram showing the configuration of the first exemplary embodiment of the present invention.

Referring to FIG. 1A, in the present embodiment, an exclusive OR circuit 1 and a 2-input AND circuit 2 having an output signal of the exclusive OR circuit 1 as one input, Another one
Two 2-input AND circuit 3 and these two AND circuits 2
And a two-input logical sum circuit 4 which receives the output signal of the logical product circuit 3.

The exclusive OR circuit 1 has one input terminal connected to the clock signal input terminal 5 and the other input terminal connected to the clock signal input terminal 6. An external clock signal CLK1 for memory access used during normal operation of the memory is input to the clock signal input terminal 5, and a clock for burn-in from outside the chip via another pin is input to the clock signal input terminal 6. Signal C
LK2 is input.

In the 2-input logical product circuit 2, one input terminal is connected to the output terminal of the exclusive OR circuit 1, and the other input terminal is connected to the test signal input terminal 7. A burn-in mode setting signal BTM generated on the chip is input to the test signal input terminal 7. The burn-in mode setting signal BTM is also used in the conventional semiconductor memory device, and when the semiconductor memory device is burned in, the power source voltage is set higher than that in the normal operation so that the power source voltage The change is detected to indicate whether the semiconductor memory device is in the normal operation mode or the burn-in mode. In the present embodiment, the burn-in mode setting signal BTM becomes low level during normal operation and becomes high level during burn-in.

In this embodiment, whether the burn-in mode is present or not is determined by the level of the burn-in mode setting signal BTM input to the test signal input terminal 7. When not in the burn-in mode, the memory is accessed by using the clock signal CLK1 input to the clock input signal terminal 5 as it is as the output clock signal CLK3. on the other hand,
When in the burn-in mode, the clock signal CLK1
And the clock signal CLK2 are exclusive-ORed to output the clock signal CLK3 having a frequency higher than that in the normal operation to access the memory. In the case of this embodiment, the memory access frequency is doubled as described below.

The circuit operation of this embodiment will be described below with reference to FIG.
This will be described with reference to the timing chart shown in (b). First, in the burn-in mode, the burn-in mode setting signal BTM becomes bilevel. As a result, since the low-level signal is input to one input terminal of the AND circuit 3, the low-level signal is always output regardless of the clock signal CLK1. On the other hand, the AND circuit 2
Since a high-level signal is input to one of the input terminals, the output signal of the exclusive OR circuit 1 is transmitted to the OR circuit 4. Since the low-level signal from the AND circuit 3 is input to one input terminal of the OR circuit 4, the output signal of the AND circuit 2, that is, the clock signal C
An exclusive OR signal of LK1 and clock signal CLK2 is output as clock signal CLK3. At this time,
As shown in (b), when the clock signal CLK1 and the clock signal CLK2 are input so that they have the same duty factor of 1/2 and the same frequency and are deviated by a half pulse width, two clock signals CLK2 are input. A clock signal CLK3 having a doubled frequency is obtained.

On the other hand, in the normal operation mode, the burn-in mode setting signal BTM becomes low level. As a result, since the low-level signal is input to one of the input terminals of the AND circuit 2, the low-level signal is always output regardless of the output signal of the exclusive OR circuit 1. On the other hand, since the high-level signal is input to one input terminal of the logical product circuit 3, the logical product circuit 3 transmits the clock signal CLK1 to the logical sum circuit 4. Since the low level from the logical product circuit 2 is input to one input terminal of the logical sum circuit 4, the output signal of the logical sum circuit 3, that is, the clock signal CL.
K1 is output as the clock signal CLK3.

As described above, according to the present embodiment, the frequency of the clock signal is switched according to the potential level of the burn-in mode setting signal BTM, and the burn-in is executed at a higher frequency than the clock signals CLK1 and CLK2. You can

Next, a second embodiment of the present invention will be described. FIG. 2A is a block diagram showing the configuration of the second exemplary embodiment of the present invention. Referring to FIG. 2A, the present embodiment differs from the first embodiment in the input signal of the AND circuit 2. In this embodiment, the clock signal OSC from the oscillation circuit 8 is input to the input terminal of the AND circuit 2 instead of the output signal of the exclusive OR circuit 1 in FIG. By the same circuit operation as in the embodiment, the clock signal CLK1 and the clock signal OSC are generated according to the potential level of the burn-in mode setting signal BTM.
One of the two is output as the clock signal CLK3. Therefore, as shown in FIG. 2B, the frequency of the clock signal OSC from the oscillation circuit 8 is set to the clock signal CLK1.
If it is set higher than the frequency of, the clock frequency during burn-in can be increased and the test can be efficiently performed. Here, since the semiconductor memory device usually has an oscillation circuit built-in on the chip for generating a clock signal having a frequency higher than the external clock signal CLK1 for memory access, if this oscillation circuit is used, the present invention can be used. It is not necessary to provide an oscillator circuit for implementation, and it is possible to reduce the number of clock signals that must be input from the outside.

[0016]

As described above, the semiconductor memory device of the present invention can access data of a plurality of words during one cycle of the external clock by switching the frequency of the memory access clock to a high frequency in the burn-in mode. It has a circuit that enables it.

As a result, according to the present invention, even if the memory has a large capacity, the same stress can be applied to the unit bit per unit bit in the same burn-in execution time as the current state.

[Brief description of drawings]

FIG. 1A is a block diagram showing a configuration of a first exemplary embodiment of the present invention. Diagram (b) is a timing chart for explaining the operation of the embodiment shown in diagram (a).

FIG. 2A is a block diagram showing a configuration of a second exemplary embodiment of the present invention. Diagram (b) is a diagram showing a timing chart for explaining the operation of the embodiment shown in diagram (a).

[Explanation of symbols] 1 exclusive OR circuit 2,3 AND circuit 4 logical OR circuit 5,6 clock signal input terminal 7 test signal input terminal 8 oscillator circuit

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location H01L 27/10 481 8728-4M

Claims (5)

[Claims] 1. A semiconductor memory device having a circuit for determining whether or not a burn-in mode is set and for switching a frequency of a memory access clock. 2. A binary control signal having a potential level corresponding to a burn-in mode and a normal operation mode, a first clock signal input from the outside, and a second clock signal input from the outside as inputs. A circuit for selecting and outputting either one of the exclusive OR signal of the first clock signal and the second clock signal and the first clock signal in accordance with the potential level of the control signal. A semiconductor memory device having. 3. An exclusive OR circuit that receives a first clock signal input from the outside and a second clock signal input from the outside to the outside, and an output signal of the exclusive OR circuit. And a first AND circuit having a binary control signal having a potential level corresponding to the burn-in mode and the normal operation mode as inputs, the first clock signal, and an inverted signal of the control signal as inputs. And a second logical product circuit for inputting the output signal of the first logical product circuit and the output signal of the second logical product circuit. Semiconductor memory device. 4. A binary control signal having a potential level corresponding to a burn-in mode and a normal operation mode, a clock signal input from the outside, and an output signal of a built-in oscillation circuit are input, and the control signal A semiconductor memory device having a circuit for selecting and outputting either one of the output signal of the oscillation circuit and the clock signal according to a potential level. 5. A first AND circuit which receives an inversion signal of a binary control signal having a potential level corresponding to a burn-in mode and a normal operation mode and a clock signal input from the outside, and the binary value. A second AND circuit that receives the control signal and the output signal of the built-in oscillation circuit, an output signal of the first AND circuit, and an output signal of the second AND circuit A semiconductor memory circuit having a circuit including a logical sum circuit having: