JPH0691426B2 - Logic circuit device - Google Patents

Description

TECHNICAL FIELD The present invention relates to a master-slave delay type logic circuit device with a set or reset function.

[Prior Art] FIG. 4 is a diagram showing a circuit configuration of a conventional master-slave delay flip-flop having a reset function.

This flip-flop is composed of a first transmission gate 31, a second transmission gate 32, a master storage unit 33, a slave storage unit 34, and an inverter 35.

The first transmission gate 31 is composed of a P-channel MOS transistor 31p and an N-channel MOS transistor 31n, and the second transmission gate 32 is a P-channel MOS transistor 3n.
2p and N-channel MOS transistor 32n. These transmission gates 31 and 33 have one conduction terminals of the P-channel MOS transistor and the N-channel MOS transistor connected to each other to serve as input terminals, and the other conduction terminals thereof to each other to serve as output terminals. Master storage unit 33
Is composed of an inverter 33a and a NOR gate 33b, and the slave storage unit 34 is a NOR gate 34a and an inverter.
It consists of 34b.

In the figure, the data input terminal 36 is connected to the input terminal of the first transmission gate 31, and the data D is applied to the data input terminal 36. The output terminal of the first transmission gate 31 is connected to the input terminal of the inverter 33a of the master storage unit 33 and the output terminal of the NOR gate 33b. The output terminal of the inverter 33a is connected to one input terminal of the NOR gate 33b and the input terminal of the second transmission gate 32. NOR gate 33b
The other input terminal is connected to the reset terminal 38, and the reset signal R is applied to the reset terminal 38.

The output terminal of the second transmission gate 32 is NO of the slave storage unit 34.
It is connected to one input terminal of the R gate 34a and the output terminal of the inverter 34b. The output terminal of the NOR gate 34a is connected to the input terminal of the inverter 34b and the data output terminal 39. The other input terminal of NOR gate 34a is the reset terminal
Connected to 38. Output data Q is derived from the data output terminal 39.

On the other hand, the clock signal CK is given to the clock terminal 40,
This clock signal CK is the P channel of the first transmission gate 31.
The first clock signal CK1 is applied to the gate terminals of the MOS transistor 31p and the N-channel MOS transistor 32n of the second transmission gate 32. Also, this clock signal CK
Is supplied as a second clock signal CK2 to the gate terminals of the N-channel MOS transistor 31n of the first transmission gate 31 and the P-channel MOS transistor 32p of the second transmission gate 32 via the inverter 35.

Next, the operation of this flip-flop will be described.

First, if the reset signal R is kept at "L" level, NO
Since the "L" level signal is input to one of the input terminals of the R gates 33b and 34a, the R gates 33b and 34a act as an inverter that inverts and outputs the signal input to the other input terminal.
In this state, when the clock signal CK becomes "L" level,
The first clock signal CK1 becomes "L" level, the second clock signal CK2 becomes "H" level, and the first transmission gate 3
1 becomes conductive. As a result, the input data D supplied to the data input terminal 36 is input to the master storage unit 33 and stored and held. At this time, the second transmission gate 32 is in a non-conducting state, and the output data Q from the data output terminal 31 does not change. Next, when the clock signal CK changes to "H" level, the first transmission gate 31 becomes non-conductive and the second transmission gate 32 becomes conductive. As a result, the data stored and held in the master storage unit 33 is input to the slave storage unit 34 and stored and held therein. As a result,
The same data as the data D given to the data input terminal 36 is output from the data output terminal 39. After this, even if the data D given to the data input terminal 36 changes, the output terminal
In the output data Q from 39, the clock signal CK is “L” next.
It is held until the level changes to “H” level.

Next, when the reset signal R is set to "H" level, the output from the NOR gate 33b of the master storage unit 33 is kept at "L" level and the output from the inverter 33a is kept at "H" level, and at the same time, the slave storage unit 34 is held. The output from the NOR gate 34a is “L”
The level and the output from the inverter 34b are maintained at the "H" level. As a result of being reset in this way, a signal of "L" level is output from the data output terminal 39 regardless of the state of the clock signal CK.

With the above operation, a delay flip-flop with a reset function is realized.

FIG. 5 is a diagram showing a circuit configuration of a conventional master-slave delay flip-flop having a set function.

This flip-flop differs from the flip-flop shown in FIG. 4 in the configurations of the master storage section 33 and the slave storage section 34, and a set terminal 37 is provided in place of the reset terminal 38. The master storage unit 33 is composed of a NOR gate 33c and an inverter 33d. One input terminal of the NOR gate 33c is connected to the output terminal of the first transmission gate 31 and the output terminal of the inverter 33d, and the other input terminal is a set terminal. Connected to 37. The output terminal of the NOR gate 33c is connected to the input terminal of the second transmission gate 32 and the input terminal of the inverter d. The slave storage unit 34 is
The input terminal of the inverter 34c is connected to the output terminal of the second transmission gate 32 and the output terminal of the NOR gate 34d, and the output terminal of the inverter 34c and the NOR gate 34d is connected to the data output terminal 39 and the NOR gate 34d. On the other hand, it is connected to the input terminal. The other input terminal of the NOR gate 34d is connected to the set terminal 37. A set signal S is given to the set terminal 37.

The normal operation of the flip-flop in response to the clock signal CK is the same as the operation of the flip-flop of FIG. 4, so the operation at the time of setting will be described.

When the set signal S is set to the “H” level, the master storage unit 33
Output from NOR gate 33c is "L" level, inverter
The output from 33d becomes "H" level, at the same time, the output from NOR gate 34d of slave storage unit 34 becomes "L" level, and the output from inverter 34c becomes "H" level. As a result of being set in this manner, a signal of "H" level is output from the data output terminal 39 regardless of the state of the clock signal CK.

By the above operation, a delay flip-flop with a set function is realized.

These flip-flops form circuits such as a register, a counter, and a shift register in the MIS type integrated circuit.

[Problems to be Solved by the Invention] In the conventional flip-flop described above, since the NOR gate is used for the master storage unit 33 and the slave storage unit 34, the number of elements increases and the area occupied by the integrated circuit is increased. However, there was a problem that the

Further, the NOR gate has a weak driving capability as compared with the inverter gate, which is disadvantageous when operating at high speed.

The present invention has been made to solve the above problems, and by configuring the data storage means by an inverting circuit, the number of elements is reduced, the driving capability is enhanced, and the operating speed is increased. Another object is to obtain a master-slave delay type logic circuit device with a set or reset function.

[Means for Solving Problems] A logic circuit device according to the present invention includes first and second switching elements, first and second memory circuits, a transistor, and a control means.

The first switching element has one conduction terminal to which an input signal is applied and the other conduction terminal. The first memory circuit includes first and second inverting circuits. The input terminal of the first inverting circuit is connected to the other conduction terminal of the first switching element. The input terminal of the second inverting circuit is connected to the output terminal of the first inverting circuit. The output terminal of the second inverting circuit is connected to the input terminal of the first inverting circuit.

The second switching element includes one conduction terminal to which the output terminal of the first inverting circuit is connected, and the other conduction terminal. The second memory circuit includes third and fourth inverting circuits. The input terminal of the third inverting circuit is connected to the other conduction terminal of the second switching element. The input terminal of the fourth inverting circuit is connected to the output terminal of the third inverting circuit.
The output terminal of the fourth inverting circuit is connected to the input terminal of the third inverting circuit.

The transistor includes a control terminal to which a predetermined control signal is applied, one conduction terminal to which the potential of one logic level is applied, and the other conduction terminal connected to the input terminal of the first inverting circuit.

The control means complementarily brings the first switching element and the second switching element into a conductive state or a non-conductive state when the transistor is in a non-conductive state. The control means also renders the first switching element non-conductive and the second switching element conductive when the transistor is conductive.

[Operation] According to the logic circuit of the present invention, when a control signal in a predetermined state is first applied to the control terminal of the transistor,
The transistor becomes non-conductive. At this time, the first and second switching elements are complementarily turned on or off by the control means. That is, when the first switching element is in the conducting state and the second switching element is in the non-conducting state, the input signal applied to one conduction terminal of the first switching element is changed to the first switching element via the first switching element. No. 1 is input to the storage circuit and stored and held. On the other hand, when the first switching element is turned off and the second switching element is turned on, the signal stored in the first storage circuit is passed through the second switching element to the second storage circuit. Is input to and stored in memory. In this state, since the first switching element is in the non-conducting state, the stored contents of the first and second memory circuits will remain even if the input signal applied to one conducting terminal of the first switching element changes. It does not change.

Next, when a control signal in another predetermined state is applied to the control terminal of the transistor, the transistor becomes conductive. At this time, the control means brings the first switching element into the non-conducting state and the second switching element into the conducting state. As a result, the potential of one logic level is input to the first memory circuit through the transistor and stored and held therein, and the output signal from the first memory circuit further passes through the second switching element to the second switching element. It is input to the memory circuit and stored and held. In this state, the first switching element is in a non-conducting state, so that even if the input signal applied to one conducting terminal of the first switching element changes, the stored contents of the first and second memory circuits are It does not change.

In this logic circuit, since the first and second memory circuits are composed of two inverting circuits, the number of elements constituting the memory circuit is reduced, and the driving ability is large and the operating speed is high. .

Embodiments Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a circuit diagram of a delay flip-flop with reset function such as CMOS according to an embodiment of the present invention.

This flip-flop includes a master latch 1, a slave latch 2, and a transmission gate control unit 3.

The master latch 1 is composed of a first transmission gate 4, a pull-down element 5 and a master storage unit 7, and the slave latch 2 is composed of a second transmission gate 8 and a slave storage unit 9. The first transmission gate 4 is composed of a P channel MOS transistor 4p and an N channel MOS transistor 4n, and the second transmission gate 8 is composed of a P channel MOS transistor 8p and an N channel MOS transistor 8n. These transmission gates 4,8 are
One conduction terminals of the P-channel MOS transistor and the N-channel MOS transistor are connected to serve as an input terminal, and the other conduction terminals thereof are connected to serve as an output terminal.

The master storage unit 7 is composed of two inverters 7a and 7b, and the slave storage unit 9 is composed of two inverters 9a and 9b. The pull-down element 5 is composed of an N-channel MOS transistor.

In the figure, the data input terminal 10 is connected to the input terminal of the first transmission gate 4, and the data D is applied to the data input terminal 10. The output terminal of the first transmission gate 4 is grounded via the pull-down element 5 and the master storage unit 7
Is connected to the input terminal of the inverter 7a and the output terminal of the inverter 7b. The output terminal of the inverter 7a is connected to the input terminal of the inverter 7b and the input terminal of the second transmission gate 8. The output terminal of the second transmission gate 8 is connected to the input terminal of the inverter 9a and the output terminal of the inverter 9b of the slave storage unit 9. The output terminal of the inverter 9a is the input terminal and data output terminal of the inverter 9b.
The output data Q is derived from the data output terminal 11.

The transmission gate controller 3 controls the first transmission gate 4, the pull-down element 5, and the second transmission gate 8. The reset signal R is applied to the reset terminal 12, and the reset signal R is applied to the gate terminal of the pull-down element 5. The reset signal R is given to one input terminal of the NOR gate 14.

On the other hand, the clock signal CK is given to the clock terminal 15,
The clock signal CK is given to the other input terminal of the NOR gate 14. The output signal from the NOR gate 14 is the inverter 16
Is inverted by the first clock signal CK1
To the gate terminals of the P-channel MOS transistor 4p of the transmission gate 4 and the N-channel MOS transistor 8n of the second transmission gate 8. The output signal from the NOR gate 14 is applied to the gate terminals of the N-channel MOS transistor 4n of the first transmission gate 4 and the P-channel MOS transistor 8p of the second transmission gate 8 as the second clock signal CK2.

In this transmission gate control unit 3, when the reset signal R is at "L" level, the NOR gate 14 functions as an inverter that inverts and outputs the signal applied to the other input terminal. Therefore, the first clock signal CK1 has the same phase as the clock signal CK, and the second clock signal CK2 has the opposite phase to the clock signal CK.

When the reset signal R is at "H" level, NOR gate 1
The output signal from 4 becomes "L" level and clock signal C
Regardless of the state of K, the first clock signal CK1 becomes "H" level and the second clock signal CK2 becomes "L" level.

Next, the operation of this flip-flop will be described.

First, the operation as a normal delay flip-flop will be described. The reset signal R is kept at the “L” level, and the reset function is disabled. At this time, the transmission gate control unit 3 functions as a clock transmission circuit and outputs the first clock signal CK1 which is a positive phase clock and the second clock signal CK2 which is a negative phase clock by the clock signal CK given to the clock terminal 15. To be done.

When the clock signal CK is at "L" level, the first clock signal CK1 is at "L" level, the second clock signal CK2 is at "H" level, the first transmission gate 4 of the master latch 1 is in the conductive state, and the slave The second transmission gate 8 of the latch 2 is turned off. This allows the data input terminal 10
The input data D given to is input to and held in the master storage unit 7. At this time, since the second transmission gate 8 is in the non-conducting state, the output data Q from the data output terminal 11 does not change. Next, when the clock signal CK changes to the “H” level, the first transmission gate 4 becomes non-conductive,
The second transmission gate 8 becomes conductive. As a result, the data stored and held in the master storage unit 7 is input to the slave storage unit 9 and stored and held therein. As a result, the same data as the data D given to the data input terminal 10 is output from the data output terminal 11. After that, even if the data D applied to the data input terminal 10 changes, the output data Q from the output terminal 11 is held until the clock signal CK next changes from "L" level to "H" level. By these operations, a normal delay flip-flop function is realized.

Next, the reset function will be described.

At the time of resetting, the reset signal R is set to the “H” level.
As a result, the first clock signal CK1 is at "H" level,
The second clock signal CK2 becomes "L" level. Therefore, the first transmission gate 4 is non-conductive and the second transmission gate 8 is conductive. At the same time, the pull-down element 5 is turned on, and the inverter 7a of the master storage unit 7 is set to "L".
A level signal is input and held. Further, the “H” level signal output from the inverter 7a is input to and held in the inverter 9a of the slave storage unit 9 via the second transmission gate 8. Then, the "L" level signal output from the inverter 9a is derived from the data output terminal 11. In this way, the master storage unit 7 and the slave storage unit 9 are forcibly reset.

At this reset, the clock signal CK is at "L" level,
Any of the "H" levels does not affect the reset operation.

FIG. 2 is a circuit diagram of a delay flip-flop with a set function according to another embodiment of the present invention.

In this flip-flop, instead of the pull-down element 5 in the flip-flop of FIG.
A pull-up element 6 composed of a MOS transistor is provided, and one input terminal of the NOR gate 14 of the transmission gate control section 3 has a set terminal 13 instead of the reset terminal 12.
Are connected. This set terminal 13 has a set signal S
Is given. The output terminal of the first transmission gate 4 is connected to the power supply line via the pull-up element 6, and a signal obtained by inverting the set signal S by the inverter 17 is applied to the gate terminal of the pull-up element 6.

The normal operation of the flip-flop in response to the clock signal CK is the same as the operation of the flip-flop of FIG. 1, so the operation at the time of setting will be described.

When the set signal S is set to "H" level, the first clock signal CK1 becomes "H" level and the second clock signal CK2 becomes "L" level. Therefore, the first transmission gate 4 is non-conductive and the second transmission gate 8 is conductive. At the same time, the pull-up element 6 is turned on, and an “H” level signal is input to and held in the master storage unit 7.

The “L” level signal output from the master storage unit 7 is input to and stored in the slave storage unit 9 via the second transmission gate 8. Then, the “H” level signal output from the slave storage unit 9 is derived from the data output terminal 11. In this way, the master storage unit 7 and the slave storage unit 9 are forcibly set.

At the time of this setting, the clock signal CK is at "L" level,
Any of the "H" levels does not affect the set operation.

Next, FIG. 3 shows an example in which a 4-bit register is constructed by the flip-flop of the embodiment shown in FIG.

In this register, one transmission gate controller 22 is connected in common to four flip-flops 21 composed of a master latch 1 and a slave latch 2 in FIG. Therefore, each flip-flop 21 operates at the same timing in response to the first clock signal CK1, the second clock signal CK2, and the reset signal R by the common transmission gate controller 22.

When the number of elements forming the flip-flop of this embodiment is compared with the number of elements forming the conventional flip-flop, the number of elements is smaller in the conventional example when one flip-flop is used, but 3 at the same timing. When one or more flip-flops are used, the transmission gate controller can be used in common, so that the number of elements is smaller in this embodiment. And as the number of flip-flops used increases, the difference in the number of elements increases,
The advantage will increase. Therefore, when the flip-flop of the present invention is used to configure a multi-bit register, a multi-stage shift register, or the like that operates at the same timing, the number of elements can be reduced.

Although FIG. 3 shows the case in which the register unit is configured using the flip-flop with the reset function of FIG. 1, the same effect is obtained when the flip-flop with the set function of FIG. 2 is used. Is obtained.

[Effects of the Invention] As described above, according to the present invention, it is possible to enhance the driving capability and increase the operating speed in the master-slave delay type logic circuit device with the set or reset function. Further, when a plurality of circuits are configured to operate at the same timing with this logic circuit device, the number of elements is reduced.

[Brief description of drawings]

1 is a circuit diagram showing an embodiment of the logic circuit device according to the present invention, FIG. 2 is a circuit diagram showing another embodiment of the logic circuit device according to the present invention, and FIG. 3 is an embodiment of FIG. FIG. 4 is a circuit diagram showing a 4-bit register configured using the same, FIG. 4 is a circuit diagram showing a conventional master-slave delay flip-flop with a reset function, and FIG. 5 is a conventional master-slave delay type with a set function. It is a circuit diagram which shows a flip-flop. In the figure, 1 is a master latch, 2 is a slave latch,
3 is a transmission gate control unit, 4 is a first transmission gate, 5 is a pull-down element, 6 is a pull-up element, 7 is a master storage unit, 8 is a second transmission gate, 9 is a slave storage unit, and 10 is data input. 11 is a data output terminal, 12 is a reset terminal, 13 is a set terminal, and 15 is a clock terminal.

Claims (1)

[Claims] 1. A first switching element having one conduction terminal to which an input signal is applied and another conduction terminal, and a first inversion having an input terminal connected to the other conduction terminal of the first switching element. A first memory circuit including a circuit and a second inverting circuit having an input terminal connected to an output terminal of the first inverting circuit and an output terminal connected to an input terminal of the first inverting circuit A second switching element having one conduction terminal to which the output terminal of the first inverting circuit is connected and the other conduction terminal, and an input terminal connected to the other conduction terminal of the second switching element A third inverting circuit, and a fourth inverting circuit having an input terminal connected to the output terminal of the third inverting circuit and an output terminal connected to the input terminal of the third inverting circuit 2 memory circuits, predetermined And a control terminal to which a control signal is applied, one conduction terminal to which a potential of one logic level is applied, and the other conduction terminal connected to the input terminal of the first inverting circuit, and the transistor, When the non-conducting state, the first switching element and the second switching element are complementarily turned on or off, and when the transistor is on, the first switching element is turned off. A logic circuit device comprising control means for turning on the second switching element.