JP2581318B2 - Semiconductor integrated circuit device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly to a semiconductor integrated circuit device having a test circuit therein.

[0002]

2. Description of the Related Art An integrated circuit device is an integrated circuit device in which thousands or tens of thousands of transistors are integrated on a chip of several mm square in a package made of plastic or ceramic. Usually, a test circuit for externally checking whether the circuit operates as designed is incorporated together with the original circuit (real circuit).
Especially for large-scale integrated circuits, whether this test can be performed reliably and in a short time not only affects product reliability but also directly affects product cost. Is an extremely important issue for some manufacturers.

FIG. 3A shows an example of a conventional test circuit.

This test circuit is disclosed in Japanese Patent Application Laid-Open No. Sho 62-15177.
No. 5, four shift registers Q1, Q4 operated by a clock φ generated inside the integrated circuit.
2, Q3 and Q4 are connected in cascade such that the Q output terminal of the previous stage is connected to the D input terminal of the next stage. The D input terminal of the first-stage shift register Q1 is connected to the test data signal T
It is connected to an external terminal to which DATA is input.

When the signals a, b, c, d, e, and f shown in FIG. 3B are input to the external terminals as the test data signal TDATA, the outputs of the shift registers Q1 to Q4 are output to the gate circuits G0, G1,. G2, G3, G4, G5 decode the test mode signals m0, m1,
m2, m3, m4, and m5 are obtained. That is, when the signal a in FIG. 3B is input to the external terminal as the test data signal TDATA, only the test mode signal m0 has an “H” pattern, and the other signals m1 to m5 have an “L” pattern. Similarly, when the signal b in FIG. 3B is input to the external terminal, only the test mode signal m1 has an "H" pattern, and the others have an "L" pattern. Similarly, only signal m2 is "H" for signal c, only signal m3 is "H" for signal d, only signal m4 is "H" for signal e,
Only the signal m5 becomes "H" for the signal f.

Another example of a conventional test circuit is disclosed in Japanese Patent Application Laid-Open No. 2-6774. As shown in FIG. 4A, the test circuit includes an n-stage shift register 10 having a plurality of data flip-flops connected in cascade.
Gates 11, 12,... One for each stage output
.. 1n are connected, a test enable signal TE is input to one input terminal of each gate, and test data TDATA and test clock T
CLK.

The shift register 10 has a test clock T
Since the data shifts from the previous stage to the next stage at the rise of CLK, the test mode signals m0, m1,.
Test data TDATA and test clock TCLK are input so that "H" data is shifted to the data flip-flop in the shift register corresponding to the expected test mode signal out of _n-1 . When data shifts to the expected data flip-flop, the test enable signal TE is set to "H", a test mode signal is input to the real circuit B, and the real circuit B is set in the test mode state.

[0008]

The latter test circuit has a problem that the number of test modes that can be set is smaller than the number of data flip-flops constituting the shift register. In the former test circuit, the test data input to the shift register is simply shifted and the gate processing is performed as it is.
If an erroneous signal is input to the input terminal of A or the input terminal of the test clock TCLK due to noise or the like, there is a risk that the test mode is entered during normal use.

An object of the present invention is to provide a test circuit for a semiconductor integrated circuit device in which a large number of test modes can be set for the number of shift registers constituting the test circuit, and there is little risk of entering the test mode easily due to noise or the like. With the goal.

[0010]

[0011]

[Means for Solving the Problems] The present invention achieves the above objects.
To start the test and test data
Shift register that can capture data and data in series
And fetching the test data from the shift register.
Out, decode the extracted test data and test
A first circuit for generating a shift mode signal;
Data from the tester to instruct the start of the test,
Generate test start instruction signal from extracted data
A second circuit, wherein the first circuit starts the test.
The test mode signal in response to an instruction signal;
To be supplied.

[0012]

[0013]

[Function] Shift register starts test data and test
Is input in series with the data indicating
When the test data is taken out from the shift register
Decode and test the test data taken together
A second circuit for generating a mode signal;
And the data for instructing the start of the test is extracted from
Generates a test start instruction signal from the extracted data,
Further, the first circuit responds to the test start instruction signal.
In response, the test mode signal is supplied to the circuit under test.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings.

FIG . 1 is a table of a test circuit of a semiconductor integrated circuit device.
It is a figure of the example explaining a notation, and the figure (a) is a semiconductor.
The circuit diagram of the test circuit of the body integrated circuit device, and the notation shown in FIG. 3B is an abbreviation of the circuit shown in FIG.

This test circuit includes a test clock TCL
N data flip-flops Q1, Q
2, Q3,..., Qn are connected to an n-stage shift register connected in cascade such that the Q output terminal of the preceding stage is connected to the D input terminal of the next stage, and the output signal Q of each data flip-flop. Logic circuits G10, G11, G12, G13,... For decoding to maximize the number of combinations
, And outputs the output of each logic circuit to test mode signals m0, m1, m2, m3,..., M (2 ⁿ -1).
And That is, in the case of an n-stage shift register, 2 ⁿ test mode signals are output. Each logic circuit G10,
One input terminal of G11, G12,... Is connected to the input terminal of the test enable signal TE, and the D input terminal of the first-stage data flip-flop Q1 of the shift register is connected to the input terminal of the test data TDATA. ing.

Next, the operation in the case of a four-stage shift register will be described.

FIG. 1D shows a timing chart. Since each data flip-flop constituting the shift register operates at the rising edge of the test clock TCLK, the rising edge of the test clock TCLK starts from the test data TDATA. A signal that changes at the falling edge is input, and test data is input to the shift register so that a desired test mode signal is decoded.

Next, when the data in the shift register has been shifted until the desired test mode signal is decoded, the test enable signal TE is set to "H" to activate the desired test mode signal. The timing chart of FIG. 1D shows a case where the test mode signals m1 and m2 are activated. Can output the 2 ⁿ test mode signal in the shift register in this example the n stages.

FIG. 2A is a circuit diagram of an embodiment of a test circuit of a semiconductor integrated circuit device according to the present invention, and FIG. 2B is a timing chart.

This embodiment is a test circuit for a six-stage shift register composed of six data flip-flops Q1 to Q6.
The output signal of Q3 is used as data for decoding in the same manner as in the example shown in FIG. 1A , and the output signals of data flip-flops Q4 to Q6 in the latter three stages are used as data for a start command. In this embodiment, a start command detection circuit (shown by a broken line in the figure ) is added to the example shown in FIG.
1 is added.

In the start command detecting circuit 1, three bits of output signals of the data flip-flops Q4 to Q6 and an inverted signal of the test clock TCLK are used as input signals.
An output terminal of the input AND gate G15 is connected to one input terminal (hereinafter, referred to as a "set input terminal") of an RS latch circuit (shown by a broken line) 1a, and a reset side of the RS latch circuit 1a. The output of the three-input NOR gate G16 (hereinafter referred to as "the output of the RS latch circuit") is input as a test enable signal TE to the logic circuits G20 to G27 for generating the test mode signals m0 to m7, and the test is performed. Clock T
The signal is input to a two-input AND gate G17 together with CLK. The output of the AND gate G17 is a signal which is input to one input terminal of the system reset signal.
An input is provided to the other input terminal of the input OR gate G18, and the output of the OR gate G18 is provided to each data flip-flop Q1 constituting the shift register.
ＱQ6 to the reset terminal R. The output of the OR gate 18 has an input terminal to which an inverted signal of the test clock TCLK is input.
Connected to the other input terminal of the input AND gate G19,
The output of the AND gate G19 is connected so as to be input to the other input terminal (hereinafter, referred to as “reset input terminal”) of the RS latch circuit 1a. A system reset signal is input to a reset input terminal of the RS latch circuit 1a.

Next, the operation will be described with reference to the timing chart shown in FIG.

As in the example shown in FIGS. 1A and 1D, the test clock TCLK is converted from the test data TDATA.
When the Q outputs of the data flip-flops Q4, Q5, and Q6 all become "H", the start command detection circuit 1 falls at the falling timing of the test clock TCLK. Is set to the set state, the output of the RS latch circuit 1a becomes "H", and the test enable signal T
Since E becomes “H”, the data flip-flops Q1 to Q1
The logic circuit that has decoded the output signal of Q3 becomes active. The timing chart of FIG. 2B shows a case where the test mode signals m2 and m1 are activated. When the test mode operation is completed during the test mode period in which the test enable signal TE is "H", the shift register is reset by the "H" signal of the next test clock TCLK, and the "L" of the test clock TCLK is reset. The signal resets the RS latch circuit 1a in the start command detection circuit 1 and returns to the initial state.

In FIG. 2B, the start command detecting circuit 1 sets all outputs of the data flip-flops Q4 to Q6 to "H".
The start command can be freely set by arbitrarily selecting the Q output and Q output of 4-Q6 and changing the logic of the gate G1. Also, by increasing the number of data flip-flops that compose the shift register, the number of bits of the start command is increased to increase the safety of entering test mode due to erroneous signals such as noise, and to increase the data for decoding circuit data. If the number of flip-flops is increased to n, the number of test modes can be easily increased to 2 ⁿ .

[0026]

As described above, according to the present invention,
Since each signal output from the shift register is decoded by a logic circuit with a predetermined logic to generate a test mode signal, a maximum of 2 ⁿ test mode signals can be generated by using n shift registers. Can be.
Further, by adding a start command detection circuit, it is possible to prevent the test mode from being easily entered due to an erroneous signal such as noise during normal use, and to enhance the safety of malfunction prevention.

[Brief description of the drawings]

FIG. 1 shows a notation of a test circuit of a semiconductor integrated circuit device .
FIG. 3A is a diagram of an example to be described, and FIG.
Circuit diagram of the test circuit, (b) shows a shorthand circuit notation shown (c), the show (d) is a timing chart.

FIG. 2A is a circuit diagram of an embodiment of a test circuit of a semiconductor integrated circuit device according to the present invention, and FIG. 2B is a timing chart.

FIG. 3A shows an example of a test circuit of a conventional semiconductor integrated circuit, and FIG. 3B shows a timing chart.

FIG. 4 shows another example of a test circuit of a conventional semiconductor integrated circuit.

[Explanation of symbols]

 Q1 to Q6, Qn Data flip-flop G15 to G19 Gate G10 to G13, G20 to G27 Logic circuit m0 to m7 Test mode signal TDATA Test data TCLK Test clock TE Test enable signal

Claims (2)

(57) [Claims] A shift register for serially fetching test data and data for instructing test start; fetching the test data from the shift register; decoding the fetched test data to a test mode; has a first circuit for generating a signal, retrieves the data indicating the test start from the shift register, and a second circuit for generating a test start signal from the retrieved data, wherein the first circuit In response to the test start instruction signal
A semiconductor integrated circuit device for supplying the test mode signal to a circuit under test . 2. The method according to claim 1, wherein the shift register includes a plurality of data free registers.
The semiconductor integrated circuit device according to claim 1, wherein flip-flops are connected in cascade .