JPH11311657A - Semiconductor-testing device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor-testing device that can be miniaturized and whose costs can be reduced by simplifying a circuit configuration. SOLUTION: An output signal A8 from a device 8 to be measured, that is obtained by executing processing based on an input test signal A7, is converted to a logic value by a comparator 7 and is sampled by a sampling circuit 43 at a timing based on a strobe A12. An output signal when the testing of an up/down counter 44 for performing counting operation by each leading edge of an output signal A10 being sampled is compared with an expectation value that is stored at a storage medium in a coincidence circuit 45, thus determining whether or not the device 8 to be measured is appropriate.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor test apparatus for inputting a test signal to a semiconductor device, causing the semiconductor device to execute a process, and determining the quality of the semiconductor device based on the obtained processing result.

[0002]

2. Description of the Related Art In recent years, the use of ICs (Integrated Circuits) in circuits used in various electronic devices has been rapidly advanced. IC, LSI (Large Scale Integrated)
circuit) implements the function of each element such as a resistor, a capacitor, and a transistor by a circuit formed by printing, vapor deposition, etc., but there is a slight variation in characteristics between mass-produced products. Occurs. Such an I
An apparatus for testing whether the characteristics of a semiconductor such as C or LSI satisfies a standard is a semiconductor test apparatus.

FIG. 2 is a block diagram showing a circuit configuration of a conventional semiconductor test apparatus 100. In FIG. 2, a semiconductor test apparatus 100 for testing a device under test 10 which is a semiconductor as a test target includes a timing control unit 2, a pattern control unit 3, a driver / comparator unit 5,
And a format control unit 9.

The timing control unit 2 includes a reference clock signal B1, a timing edge B2, and a strobe edge B
3 is generated. Then, the timing control unit 2 outputs the reference clock signal B1 to the pattern control unit 3 and the pattern memory unit 91 in the format control unit 9 to control the operation timing of each unit. In addition, the timing control unit 2 outputs the timing edge B2 to the formatter 92 in the format control unit 9 and outputs the strobe edge B3 (a signal that defines a time position when judging pass / fail) in the format control unit 9. Output to the judgment circuit 93.

The pattern control section 3 generates a pattern address signal B4 and, based on the timing of the reference clock signal B1 input from the timing control section 2, converts the pattern address signal B4 into a pattern memory section 91 in the format control section 9. Output to

As shown in FIG. 2, the format control unit 9 comprises a pattern memory unit 91, a formatter 92, and a judgment circuit 93. The format control unit 9 performs waveform shaping of an input test signal for testing the device under test 10, Device 1
Device under test 10 based on the signal output by 0
Is determined.

The pattern memory unit 91 stores the device under test 1
It stores various pattern data for testing 0 and the expected value of the processing result obtained when the device under test 10 executes the processing based on each pattern data. Then, the pattern memory unit 91 operates based on the timing of the reference clock signal B1 input from the timing control unit 2, and is stored at the address specified by the pattern address signal B4 input from the pattern control unit 3. The pattern data is read and transmitted to the formatter 92 as pattern data B5, and the corresponding expected value is read and transmitted to the determination circuit 93 as the expected value B10.

The formatter 92 includes a pattern memory unit 91
Data B5 input from the controller and the timing controller 2
And generates an input test signal B6 based on the timing edge B2 input from the controller 6 and outputs it to the driver 6 in the driver / comparator unit 5.

The driver / comparator unit 5 includes a driver 6 and a comparator 7 as shown in FIG. 2, and performs a predetermined signal processing as an interface between the format control unit 9 and the device under test 10.

The driver 6 performs a predetermined conversion on the input test signal B6 input from the formatter 92 in the format control section 9, and outputs it to the device under test 10 as an input test signal B7.

The device under test 10 executes a process based on the input test signal B7 input from the driver 6 in the driver / comparator unit 5, and outputs an output signal B8 as an execution result in the driver / comparator unit 5. Output to the comparator 7.

The comparator 7 compares the output signal B8 input from the device under test 10 with a preset reference voltage value, converts the comparison result into a logical value, and outputs the output signal B8.
9 is output to the determination circuit 93 in the format control unit 9.

Further, a determination circuit 93 in the format control unit 9 receives an output signal B9 input from the comparator 7 and an input from the pattern memory unit 91 based on the timing of the strobe edge B3 input from the timing control unit 2. It is determined whether the expected value B10 matches the expected value B10, and a pass / fail determination result B11 of the device under test 10 is output to the control device.

By the processing of each unit as described above, the semiconductor test apparatus 100 inputs a test signal to the device under test 10, causes the device to perform processing based on the input test signal, and outputs the signal from the device under test 10. By comparing the signal as the processing result with the expected value, it can be determined whether or not the device under test 10 is a non-defective product.

[0015]

However, in the conventional semiconductor test apparatus 100 shown in FIG. 2, a pass / fail judgment is made by comparing a signal output from the device under test 10 with an expected value. Is indispensable, but since this determination circuit 93 has a complicated circuit configuration,
The circuit configuration of the entire semiconductor test apparatus 100 has become complicated.

Further, when testing the device under test 10 having a plurality of output terminals, it is necessary to provide the determination circuit 93 for all the output terminals. It has been difficult to reduce the size of the 100, or the cost has been increased.

An object of the present invention is to provide a semiconductor test apparatus capable of reducing the size and cost by simplifying the circuit configuration.

[0018]

According to the first aspect of the present invention,
A semiconductor test apparatus that generates a test signal for testing a device under test, outputs the signal to the device under test, and analyzes the state of an output signal of the device under test with respect to the test signal to test the device under test. A conversion unit that converts an output signal of the device under test to a logical value based on a result of comparing a voltage value of an output signal of the device under test with a preset reference voltage; and Sampling means for sampling an input logical value at a predetermined timing; counting means for performing a counting operation based on either a rising edge or a falling edge of the logical value sampled by the sampling means; At the end of the test on the measuring device, the count value output from the counting means is stored as an expected value. It is characterized by comprising: a quality determining means for performing a quality determination of the measured device by comparing the count value output from said counting means value and at study termination.

According to the semiconductor test apparatus of the present invention, a test signal for testing the device under test is generated and output to the device under test, and the conversion unit converts the test signal to the device under test with respect to the test signal. The output signal of the device under test is converted into a logical value based on a result of comparing the output signal of the device with a preset reference voltage, and the logical value input from the converting means is converted by a sampling means to a predetermined timing. The counting is performed by the counting means, and the counting operation is performed based on either the rising edge or the falling edge of the logical value sampled by the sampling means. The count value output from the counting means is stored as an expected value. Performing quality determination of the measured device by comparing the count value output from the counting means.

Therefore, an output serving as a criterion for determination can be obtained by a sampling means and a counting means having a small number of parts and a simple circuit configuration as compared with a conventional judgment circuit, and the comparison with an expected value is made by a good / bad judgment means. Therefore, the size of the entire semiconductor test apparatus can be reduced, and the cost for manufacturing the semiconductor test apparatus can be reduced. Further, if the logic values output from the counting means are sequentially stored in the pass / fail judgment means at the end of the test, there is no necessity of performing real-time judgment as in the conventional judgment circuit, so that all semiconductor tests have been completed. It is also possible to perform the determination process all at once, and the efficiency of the semiconductor test by the semiconductor test device can be improved.

According to a second aspect of the present invention, in the semiconductor test apparatus according to the first aspect, the counting means includes:
The count value in the initial state is set to “0”, and the count value may be an addition counter that performs a counting operation by addition based on either a rising edge or a falling edge of the logical value sampled by the sampling unit. .

According to the semiconductor test apparatus of the second aspect of the present invention, the effect of the first aspect of the present invention can be easily realized by an addition counter realized by a circuit having a simple configuration.

According to a third aspect of the present invention, in the semiconductor test apparatus according to the first aspect, the counting means includes:
The initial state is set so that the output at the time when the test is completed has a predetermined count value, and the pass / fail determination means determines the predetermined count value and the count value output from the change state detection means at the end of the test. It is effective to judge the quality of the device under test by comparing.

According to the third aspect of the present invention, in addition to the effects of the first aspect, the pass / fail judgment means always compares the predetermined count value in various semiconductor tests. Since it suffices to store the expected value, it is not necessary to store the expected value, and the semiconductor test by the semiconductor test apparatus can be more easily executed.

According to a fourth aspect of the present invention, in the semiconductor test apparatus according to the third aspect, the counting means is set in an initial state so that the predetermined count value becomes "0", and the sampling means performs sampling. It may be a subtraction counter that performs a counting operation by subtraction based on either the rising edge or the falling edge of the logical value.

According to the semiconductor test apparatus of the fourth aspect of the present invention, the effect of the third aspect of the present invention can be easily realized by a subtraction counter realized by a circuit having a simple configuration.

[0027]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, an embodiment of a semiconductor test apparatus according to the present invention will be described in detail with reference to FIG.

First, the configuration will be described.

FIG. 1 is a block diagram showing a circuit configuration of a semiconductor test apparatus 1 according to the present embodiment. In FIG. 1, a semiconductor test apparatus 1 for testing a device under test 8 which is a semiconductor as a test object includes a timing control unit 2, a pattern control unit 3, a format control unit 4,
And a driver / comparator unit 5. 1, the same components as those of the conventional semiconductor test apparatus 100 are denoted by the same reference numerals as those of the semiconductor test apparatus 100 shown in FIG.

The timing control unit 2 outputs a test start signal A
1 starts to operate, and the reference clock signal A
2. Generate timing edge A3 and strobe A12. Then, the timing control section 2 outputs the reference clock signal A2 to the pattern control section 3 and the pattern memory section 41 in the format control section 4 to control the operation timing of each section. Further, the timing control unit 2 outputs the timing edge A3 to the formatter 42 in the format control unit 4, and outputs the strobe A12
Is output to the sampling circuit 43 in the format control unit 4.

The pattern control unit 3 starts operation when the test start signal A1 is input, generates a pattern address signal A4, and generates a pattern address signal A4 based on the timing of the reference clock signal A2 input from the timing control unit 2. The address signal A4 is output to the pattern memory unit 41 in the format control unit 4.

As shown in FIG. 1, the format control section 4 comprises a pattern memory section 41, a formatter 42, a sampling circuit 43, an up / down counter 44, and a coincidence circuit 45, and an input for testing the device under test 8. The waveform shaping of the test signal and the quality judgment of the device under test 8 based on the signal output by the device under test 8 are performed.

The pattern memory section 41 stores the device under test 8
It stores various pattern data for testing. Then, when the test start signal A1 is input, the pattern memory unit 41 operates based on the timing of the reference clock signal A2 input from the timing control unit 2, and the pattern address signal A4 input from the pattern control unit 3. The pattern data stored at the address designated by the command is read and transmitted to the formatter 42 as pattern data A5.

The formatter 42 outputs a test start signal A1
Is started, an input test signal A6 is generated based on the pattern data A5 input from the pattern memory unit 41 and the timing edge A3 input from the timing control unit 2, and the driver / comparator unit 5 Is output to the driver 6 within.

The sampling circuit 43 starts operating when the test start signal A1 is input, and outputs the output signal A input from the comparator 7 in the driver / comparator unit 5.
9 is the strobe A input from the timing control unit 2.
Sampling is performed based on the timing of No. 12 and output to the up / down counter 44 as an output signal A10.

The up / down counter 44 sets the count value to “0” as an initial setting when the test start signal A 1 is input, and then counts up at every rising edge of the output signal A 10 input from the sampling circuit 43. The up operation is performed, and the count value at the end of the test is output to the matching circuit 45.

The matching circuit 45 includes a storage medium,
In this storage medium, the count value output from the up / down counter 44 when a good device under test is tested is stored in advance as an expected value. And the matching circuit 4
5 starts the operation when the test start signal A1 is input, and compares the count value input from the up / down counter 44 with the expected value of the count value stored in the storage medium at the end of the test. By this, the quality of the device under test 8 is determined.

The driver / comparator unit 5 includes a driver 6 and a comparator 7 as shown in FIG. 1, and performs predetermined signal processing as an interface between the format control unit 4 and the device under test 8.

The driver 6 performs a predetermined conversion on the input test signal A6 input from the formatter 42 in the format control section 4 and outputs the converted signal to the device under test 8 as an input test signal A7.

The comparator 7 compares the output signal A8 input from the device under test 8 with a preset reference voltage value, converts the comparison result to a logical value, and outputs the output signal A4
As the sampling circuit 43 in the format control unit 4.
Output to

The device under test 8 receives the input test signal A input from the driver 6 in the driver / comparator unit 5.
7 and the output signal A as the execution result
8 is output to the comparator 7 in the driver / comparator unit 5.

Next, the operation will be described.

First, when a test start signal A1 is input from the outside, each of the timing control unit 2, the pattern control unit 3, and the format control unit 4 starts operating. That is, the timing control unit 2 outputs the reference clock signal A2
Is generated and output to the pattern control unit 3 and the pattern memory unit 41 in the format control unit 4. The pattern control unit 3 generates a pattern address signal A4 and outputs the reference clock input from the timing control unit 2. Based on the timing of the signal A2, the pattern address signal A
4 is output to the pattern memory unit 41 in the format control unit 4. The up / down counter 44 sets the count value to “0” as an initial setting.

The pattern memory section 41 operates based on the timing of the reference clock signal A2 input from the timing control section 2, and the pattern control section 3
And reads the pattern data stored at the address specified by the pattern address signal A4 input from the controller and transmits the pattern data to the formatter 42 as pattern data A5. Further, the timing control unit 2 outputs the timing edge A
3 is generated and output to the formatter 42.

The formatter 42 includes a pattern memory unit 41
The input test signal A6 is generated based on the pattern data A5 input from the controller 3 and the timing edge A3 input from the timing controller 2, and the driver / comparator 5
The driver 6 performs a predetermined conversion on the input test signal A6 to output the input test signal A6.
7 to the device under test 8.

The device under test 8 which has received the input test signal A7 from the driver 6 performs predetermined processing based on the signal pattern of the input test signal A7, and outputs a signal as the processing result as an output signal A8 to the comparator 7 The comparator 7 compares the output signal A8 with a preset reference voltage value, converts the comparison result into a logical value, and outputs the result to the sampling circuit 43 in the format control unit 4 as an output signal A4. Output.

Further, the timing control unit 2 has a strobe A1 which is a signal for defining a time position when judging pass / fail.
2 is output to the sampling circuit 43. In other words, the timing control unit 2 considers the processing performed by the device under test 8 based on the input test signal A7 and the time lag determined by the length of each transmission path through which various signals are conducted. Is determined by the sampling circuit 43 by the strobe A12.

Then, the sampling circuit 43 samples the output signal A9 input from the comparator 7 based on the timing of the strobe A12 input from the timing control unit 2, and outputs the output signal A10 to the up / down counter 44. Output. Further, the up-down counter 44 performs a count-up operation at every rising edge of the output signal A10 input from the sampling circuit 43, and outputs the count value at the end of the test to the coincidence circuit 45. Further, the coincidence circuit 45 compares the count value input from the up / down counter 44 at the end of the test with the expected value of the count value stored in the storage medium, thereby determining the quality of the device under test 8. Do.

That is, the up / down counter 44
Since the count-up operation is performed for each rising edge of the input output signal A10, the test is performed by using the output signal A10 indicating the output pattern of the device under test 8 that performs processing based on the waveform of the input test signal A7 determined by the pattern data A5. The value of the count value at the end can be specified by performing a test on a good device under test 8 in advance. Then, the count value of the good device under test 8 at the end of the test is stored as an expected value in a storage medium in the matching circuit 45. At the end of the test, the output signal of the up / down counter 44 is
The quality of the device under test 8 can be determined by comparing it with an expected value stored in advance.

As described above, according to the semiconductor test apparatus 1 of the present embodiment, the output signal A8 from the device under test 8 obtained by executing the processing based on the input test signal A7 is output by the comparator 7. After being converted to a logical value, the output signal at the end of the test of the up / down counter 44, which performs sampling at each rising edge of the sampled output signal A10, is sampled by the sampling circuit 43 at a timing based on the strobe A12. The quality of the device under test 8 is determined by comparing the measured value with the expected value stored in the storage medium in the circuit 45.

Therefore, the sampling circuit 4 has a smaller number of parts and a simpler circuit configuration than the conventional judgment circuit.
3. An output serving as a criterion for determination can be obtained by the up / down counter 44, and the comparison with the expected value is performed in the matching circuit 45. 1 can be reduced in cost.

Further, since it is not necessary to make a real-time judgment unlike the conventional judgment circuit, the output signal of the up / down counter 44 at the end of the test is sequentially stored in the storage medium in the coincidence circuit 45, and the whole semiconductor test is performed. Since it is possible to perform the determination processing all at once after the completion, the efficiency of the semiconductor test by the semiconductor test apparatus 1 can be improved.

The up / down counter 44 of the semiconductor test apparatus 1 in the above embodiment has a count value set to “0” as an initial setting and performs a count-up operation. The count value as an initial setting may be set so that the output signal at the time of termination is “0”.

In this case, since the expected value is always "0", the matching circuit 45 does not need to store the expected value.
The semiconductor test by the semiconductor test apparatus 1 can be performed more easily.

[0055]

According to the first aspect of the present invention, an output serving as a reference for determination can be obtained by the sampling means and the counting means having a smaller number of parts and a simple circuit configuration as compared with the conventional determination circuit. Since the comparison with the expected value is performed by the pass / fail determination means, it is possible to reduce the size of the entire semiconductor test apparatus and reduce the cost of manufacturing the semiconductor test apparatus. Further, if the logic values output from the counting means are sequentially stored in the pass / fail judgment means at the end of the test, there is no necessity of performing real-time judgment as in the conventional judgment circuit, so that all semiconductor tests have been completed. It is also possible to perform the determination process all at once, and the efficiency of the semiconductor test by the semiconductor test device can be improved.

According to the second aspect of the invention, the effect of the first aspect of the invention can be easily realized by the addition counter realized by a circuit having a simple configuration.

According to the third aspect of the present invention, in addition to the effect of the first aspect of the present invention, the pass / fail judgment means only needs to always compare the predetermined count value in various semiconductor tests. It is not necessary to store the expected value, and the semiconductor test by the semiconductor test apparatus can be more easily executed.

According to the fourth aspect of the present invention, the effect of the third aspect of the present invention can be easily realized by a subtraction counter realized by a circuit having a simple configuration.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a circuit configuration of a semiconductor test apparatus 1 according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a circuit configuration of a conventional semiconductor test apparatus 100.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Semiconductor test apparatus 2 Timing control part 3 Pattern control part 4 Format control part 41 Pattern memory part 42 Formatter 43 Sampling circuit 44 Up / down counter 45 Matching circuit 5 Driver / comparator part 6 Driver 7 Comparator 8 Device under test 9 Format control part 10 Device under test

Claims (4)

[Claims] 1. A test of a device under test by generating a test signal for testing the device under test, outputting the signal to the device under test, and analyzing a state of an output signal of the device under test with respect to the test signal. Conversion means for converting the output signal of the device under test to a logical value based on the result of comparing the voltage value of the output signal of the device under test with a preset reference voltage. Sampling means for sampling a logical value input from the converting means at a predetermined timing; and counting means for performing a counting operation based on either a rising edge or a falling edge of the logical value sampled by the sampling means. And a count value output from the counting means at the end of the test on a good device under test as an expected value. Storing and comparing the expected value with the count value output from the counting means at the end of the test to determine the quality of the device under test. . 2. The counting means sets a count value in an initial state to "0", and performs a counting operation by addition based on either a rising edge or a falling edge of a logical value sampled by the sampling means. 2. The semiconductor test apparatus according to claim 1, wherein the semiconductor test apparatus is an addition counter that performs the following. 3. An initial state is set so that an output at the time when the test is completed has a predetermined count value.
2. The semiconductor according to claim 1, wherein the pass / fail judgment unit judges pass / fail of the device under test by comparing the predetermined count value with a count value output from the count unit at the end of a test. Testing equipment. 4. The counting means has an initial state set so that the predetermined count value becomes "0", and is provided at either a rising edge or a falling edge of a logical value sampled by the sampling means. 4. The semiconductor test apparatus according to claim 3, wherein the semiconductor test apparatus is a subtraction counter that performs a counting operation by subtraction based on the subtraction counter.