JPH02840U - - Google Patents

Info

Publication number
JPH02840U
JPH02840U JP7724188U JP7724188U JPH02840U JP H02840 U JPH02840 U JP H02840U JP 7724188 U JP7724188 U JP 7724188U JP 7724188 U JP7724188 U JP 7724188U JP H02840 U JPH02840 U JP H02840U
Authority
JP
Japan
Prior art keywords
signal
reset
timing
opposite direction
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7724188U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP7724188U priority Critical patent/JPH02840U/ja
Publication of JPH02840U publication Critical patent/JPH02840U/ja
Pending legal-status Critical Current

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  • Pulse Circuits (AREA)
  • Analogue/Digital Conversion (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本考案によるPWM信号復号回路の一
実施例を示す図、第2図及び第3図は各々クロツ
クCKの周期が変わつた場合における第1図の各
部波形を示すタイミングチヤート、第4図は本考
案の他の実施例を示す図、第5図は第4図の各部
波形を示すタイミングチヤート、第6図は従来の
構成を示す図、第7図及び第8図は各々クロツク
CKの周期が異なる場合における第6図の各部波
形を示すタイミングチヤートである。 1…リセツト回路、2…カウンタ回路、3…サ
ンプルパルス発生回路、4…サンプルホールド回
路。
FIG. 1 is a diagram showing an embodiment of the PWM signal decoding circuit according to the present invention, FIGS. 2 and 3 are timing charts showing waveforms of various parts of FIG. 1 when the period of the clock CK changes, and FIG. 5 is a timing chart showing waveforms of each part of FIG. 4, FIG. 6 is a diagram showing a conventional configuration, and FIGS. 7 and 8 are clock CK diagrams. 7 is a timing chart showing waveforms of various parts in FIG. 6 when the periods of the signals are different. 1...Reset circuit, 2...Counter circuit, 3...Sample pulse generation circuit, 4...Sample hold circuit.

Claims (1)

【実用新案登録請求の範囲】 PWM信号の立上り又は立下りを検出してリセ
ツト信号を出力するリセツト回路と、 前記リセツト信号によつてクロツクに基づくカ
ウント動作を開始すると共に、リセツト信号出力
後のPWM信号の反転により逆方向にカウント動
作するカウンタ回路とを備え、 前記リセツト信号のタイミングと、前記カウン
タ回路のカウント値が前記逆方向のカウント動作
時において所定値となるタイミングとにより復号
信号を得るように構成した、 ことを特徴とするPWM信号復号回路。
[Claims for Utility Model Registration] A reset circuit that detects the rising or falling edge of a PWM signal and outputs a reset signal; A counter circuit that performs a counting operation in the opposite direction by inversion of a signal is provided, and a decoded signal is obtained based on the timing of the reset signal and the timing at which the count value of the counter circuit reaches a predetermined value during the counting operation in the opposite direction. A PWM signal decoding circuit configured as follows.
JP7724188U 1988-06-13 1988-06-13 Pending JPH02840U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7724188U JPH02840U (en) 1988-06-13 1988-06-13

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7724188U JPH02840U (en) 1988-06-13 1988-06-13

Publications (1)

Publication Number Publication Date
JPH02840U true JPH02840U (en) 1990-01-05

Family

ID=31302238

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7724188U Pending JPH02840U (en) 1988-06-13 1988-06-13

Country Status (1)

Country Link
JP (1) JPH02840U (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02151119A (en) * 1988-12-02 1990-06-11 Yaskawa Electric Mfg Co Ltd Pulse width modulation signal demodulation circuit
JPH03126818U (en) * 1990-04-02 1991-12-20
JPH0767191A (en) * 1991-05-24 1995-03-10 Rockwell Internatl Corp Exchange interface system and communication method of synchronous digital data communication network

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02151119A (en) * 1988-12-02 1990-06-11 Yaskawa Electric Mfg Co Ltd Pulse width modulation signal demodulation circuit
JPH03126818U (en) * 1990-04-02 1991-12-20
JPH0767191A (en) * 1991-05-24 1995-03-10 Rockwell Internatl Corp Exchange interface system and communication method of synchronous digital data communication network

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