JPS61192349U - - Google Patents
Info
- Publication number
- JPS61192349U JPS61192349U JP7457585U JP7457585U JPS61192349U JP S61192349 U JPS61192349 U JP S61192349U JP 7457585 U JP7457585 U JP 7457585U JP 7457585 U JP7457585 U JP 7457585U JP S61192349 U JPS61192349 U JP S61192349U
- Authority
- JP
- Japan
- Prior art keywords
- carry
- output
- absolute value
- adder
- clock pulse
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000001514 detection method Methods 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 6
Description
第１図は本考案になる絶対値器の原理的構成図
、第２図はその実施例図、第３図は本考案実施例
のクロツクパルスの波形と加算動作のタイミング
を示す図、第４図は従来の絶対値器の原理的構成
図、第５図はその実施例図である。
１……加算器、２……反転ゲート、３……排他
的論理和回路、４……Ｄフリツプ―フロツプ、５
……ＯＲゲート、６……キヤリー検出用アダー、
７……キヤリー出力、８……加算器出力、９……
キヤリー加算用アダー、１０……クロツク。
Fig. 1 is a diagram showing the basic configuration of the absolute value device according to the present invention, Fig. 2 is a diagram showing its embodiment, Fig. 3 is a diagram showing the waveform of the clock pulse and the timing of the addition operation in the embodiment of the present invention, and Fig. 4 is a diagram showing the timing of the addition operation. 5 is a diagram showing the basic configuration of a conventional absolute value device, and FIG. 5 is a diagram showing an embodiment thereof. 1...Adder, 2...Inverting gate, 3...Exclusive OR circuit, 4...D flip-flop, 5
...OR gate, 6...Adder for carry detection,
7...Carry output, 8...Adder output, 9...
Adder for carry addition, 10... clock.
Claims (1)
用して求める絶対値器において、クロツクパルス
１０の前半では、デイジタル入力信号とキヤリー
検出用アダー６としての前記クロツクパルス１０
の１とを加算し、当該加算後キヤリーが生じれば
キヤリー出力７に出力し、前記クロツクパルス１
０の後半では、前記キヤリー出力７をそれまで保
持して前記キヤリー検出用アダー６へ帰還し、前
記デイジタル入力信号と再び加算し、当該再び加
算後のキヤリー出力７の反転値と当該再び加算後
のデイジタル出力信号８との排他的論理和処理３
をとつて、前記差分絶対値を求めることを特徴と
する絶対値器。 In the absolute value device which calculates the absolute value of the difference between two digital values using an adder, in the first half of the clock pulse 10, the digital input signal and the clock pulse 10 as the adder 6 for carry detection are used.
If a carry occurs after the addition, it is output to the carry output 7, and the clock pulse 1 is outputted to the carry output 7.
In the second half of 0, the carry output 7 is held until then and returned to the carry detection adder 6, and is added to the digital input signal again, and the inverted value of the carry output 7 after the addition is obtained. Exclusive OR processing 3 with the digital output signal 8 of
An absolute value device characterized in that the absolute value of the difference is obtained by taking the following.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7457585U JPS61192349U (en) | 1985-05-20 | 1985-05-20 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7457585U JPS61192349U (en) | 1985-05-20 | 1985-05-20 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61192349U true JPS61192349U (en) | 1986-11-29 |
Family
ID=30615006
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7457585U Pending JPS61192349U (en) | 1985-05-20 | 1985-05-20 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61192349U (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5320833A (en) * | 1976-08-11 | 1978-02-25 | Seiko Epson Corp | Absolute value arithmetic circuit |
| JPS55121483A (en) * | 1979-03-07 | 1980-09-18 | Ibm | Absolute difference generation mechanism |
| JPS60156139A (en) * | 1984-01-25 | 1985-08-16 | Nec Corp | Absolute difference calculating circuit |
-
1985
- 1985-05-20 JP JP7457585U patent/JPS61192349U/ja active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5320833A (en) * | 1976-08-11 | 1978-02-25 | Seiko Epson Corp | Absolute value arithmetic circuit |
| JPS55121483A (en) * | 1979-03-07 | 1980-09-18 | Ibm | Absolute difference generation mechanism |
| JPS60156139A (en) * | 1984-01-25 | 1985-08-16 | Nec Corp | Absolute difference calculating circuit |
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