JPH02122374U - - Google Patents

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Publication number
JPH02122374U
JPH02122374U JP3043289U JP3043289U JPH02122374U JP H02122374 U JPH02122374 U JP H02122374U JP 3043289 U JP3043289 U JP 3043289U JP 3043289 U JP3043289 U JP 3043289U JP H02122374 U JPH02122374 U JP H02122374U
Authority
JP
Japan
Prior art keywords
circuit
frequency difference
conversion
difference signal
timing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3043289U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP3043289U priority Critical patent/JPH02122374U/ja
Publication of JPH02122374U publication Critical patent/JPH02122374U/ja
Pending legal-status Critical Current

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  • Radar Systems Or Details Thereof (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案の一実施例のブロツク図である
。 1……カウンタ回路、2……A/D変換回路、
3……タイミング発生回路、4……信号処理回路
FIG. 1 is a block diagram of one embodiment of the present invention. 1...Counter circuit, 2...A/D conversion circuit,
3...timing generation circuit, 4...signal processing circuit.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 周波数差信号のゼロクロスポイントをカウント
するカウンタ回路と、周波数差信号をサンプルし
てデイジタル信号として出力するA/D変換回路
と、カウンタ回路の出力タイミング及びA/D変
換回路の変換タイミングを発生させるタイミング
発生回路と、カウンタ回路とA/D変換回路から
のデイジタル信号を入力して演算処理を行い周波
数差信号の積分値を一定時間間隔毎に出力する信
号処理回路とを備えることを特徴とするドツプラ
計測回路。
A counter circuit that counts zero crossing points of a frequency difference signal, an A/D conversion circuit that samples the frequency difference signal and outputs it as a digital signal, and a timing that generates the output timing of the counter circuit and the conversion timing of the A/D conversion circuit. A Doppler characterized by comprising a generation circuit and a signal processing circuit which inputs digital signals from a counter circuit and an A/D conversion circuit, performs arithmetic processing, and outputs an integral value of a frequency difference signal at regular time intervals. Measurement circuit.
JP3043289U 1989-03-17 1989-03-17 Pending JPH02122374U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3043289U JPH02122374U (en) 1989-03-17 1989-03-17

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3043289U JPH02122374U (en) 1989-03-17 1989-03-17

Publications (1)

Publication Number Publication Date
JPH02122374U true JPH02122374U (en) 1990-10-05

Family

ID=31255496

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3043289U Pending JPH02122374U (en) 1989-03-17 1989-03-17

Country Status (1)

Country Link
JP (1) JPH02122374U (en)

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