JPS6344166U - - Google Patents
Info
- Publication number
- JPS6344166U JPS6344166U JP13836186U JP13836186U JPS6344166U JP S6344166 U JPS6344166 U JP S6344166U JP 13836186 U JP13836186 U JP 13836186U JP 13836186 U JP13836186 U JP 13836186U JP S6344166 U JPS6344166 U JP S6344166U
- Authority
- JP
- Japan
- Prior art keywords
- comparator
- level data
- input terminal
- control section
- clock generator
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Testing Or Calibration Of Command Recording Devices (AREA)
- Measurement Of Unknown Time Intervals (AREA)
- Measuring Frequencies, Analyzing Spectra (AREA)
- Measurement Of Current Or Voltage (AREA)
Description
第１図は本考案の一実施例を示す回路図、第２
図は本考案の他の実施例を示す回路図である。
１…基準クロツク発生器、２…コンパレータ、
３…カウンタ、４…演算制御部、５…Ｄ／Ａ変換
器、６…逐次比較レジスタ、７…マルチプレクサ
。
Figure 1 is a circuit diagram showing one embodiment of the present invention;
The figure is a circuit diagram showing another embodiment of the present invention. 1...Reference clock generator, 2...Comparator,
3... Counter, 4... Arithmetic control unit, 5... D/A converter, 6... Successive approximation register, 7... Multiplexer.
Claims (1)
パレータと、 基準クロツク発生器から出力されるクロツクを
コンパレータの出力信号に従つてカウントするカ
ウンタと、 電圧測定時にはコンパレータの出力信号に基づ
いて基準レベルデータを出力し、時間測定時には
所定のトリガレベルデータを出力する演算制御部
と、 演算制御部から加えられる基準レベルデータお
よびトリガレベルデータをアナログ信号に変換し
てコンパレータの他方の入力端子に加えるＤ／Ａ
変換器、 とで構成されたことを特徴とするデジタル測定装
置。[Claims for Utility Model Registration] A reference clock generator, a comparator to which a signal under test is applied to one input terminal, a counter that counts the clock output from the reference clock generator according to the output signal of the comparator; A calculation control section that outputs reference level data based on the comparator output signal when measuring voltage, and outputs predetermined trigger level data when measuring time, and converts the reference level data and trigger level data added from the calculation control section into analog signals. D/A converted and added to the other input terminal of the comparator
A digital measuring device comprising: a converter;
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13836186U JPS6344166U (en) | 1986-09-09 | 1986-09-09 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13836186U JPS6344166U (en) | 1986-09-09 | 1986-09-09 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6344166U true JPS6344166U (en) | 1988-03-24 |
Family
ID=31043272
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13836186U Pending JPS6344166U (en) | 1986-09-09 | 1986-09-09 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6344166U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003534702A (en) * | 2000-05-24 | 2003-11-18 | インフィネオン テヒノロギーズ アーゲー | Apparatus and method for confirming reception of signal of predetermined frequency |
-
1986
- 1986-09-09 JP JP13836186U patent/JPS6344166U/ja active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003534702A (en) * | 2000-05-24 | 2003-11-18 | インフィネオン テヒノロギーズ アーゲー | Apparatus and method for confirming reception of signal of predetermined frequency |
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