JPS6442625U - - Google Patents

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Publication number
JPS6442625U
JPS6442625U JP1987137073U JP13707387U JPS6442625U JP S6442625 U JPS6442625 U JP S6442625U JP 1987137073 U JP1987137073 U JP 1987137073U JP 13707387 U JP13707387 U JP 13707387U JP S6442625 U JPS6442625 U JP S6442625U
Authority
JP
Japan
Prior art keywords
signal
comparator
compares
magnitude
differential
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1987137073U
Other languages
Japanese (ja)
Other versions
JPH0727694Y2 (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1987137073U priority Critical patent/JPH0727694Y2/en
Publication of JPS6442625U publication Critical patent/JPS6442625U/ja
Application granted granted Critical
Publication of JPH0727694Y2 publication Critical patent/JPH0727694Y2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案に係る可変デイレイ回路の一実
施例を示した図、第2図は第1図各部の信号のタ
イムチヤート、第3図は本考案の別の構成例を示
す図、第4図は第3図回路の各部の信号のタイム
チヤート、第5図は従来例を示す図、第6図は第
5図各部の信号のタイムチヤートである。 1……バツフア、6,7,12……コンパレー
タ、21〜24……積分器。
FIG. 1 is a diagram showing an embodiment of the variable delay circuit according to the present invention, FIG. 2 is a time chart of signals of each part in FIG. 1, and FIG. 3 is a diagram showing another example of the configuration of the present invention. 4 is a time chart of signals at various parts of the circuit shown in FIG. 3, FIG. 5 is a diagram showing a conventional example, and FIG. 6 is a time chart of signals at various parts of the circuit shown in FIG. 1... Buffer, 6, 7, 12... Comparator, 21-24... Integrator.

Claims (1)

【実用新案登録請求の範囲】 パルス状の入力信号を受け、差動信号a,bを
出力するバツフアと、 一方の差動信号に基づく信号bと比較電圧Vr
の大小を比べる第1のコンパレータ6と、 他方の差動信号に基づく信号eと比較電圧Vr
の大小を比べる第2のコンパレータ7と、 第1と第2のコンパレータの出力に基づく信号
g,hを導入し、これの大小を比べる第3のコン
パレータ12と、 を備えたことを特徴とする可変デイレイ回路。
[Claims for Utility Model Registration] A buffer that receives a pulsed input signal and outputs differential signals a and b, and a signal b based on one differential signal and a comparison voltage Vr.
A first comparator 6 compares the magnitude of the signal e based on the other differential signal and the comparison voltage Vr.
A third comparator 12 introduces signals g and h based on the outputs of the first and second comparators and compares the magnitude thereof. Variable delay circuit.
JP1987137073U 1987-09-08 1987-09-08 Variable delay circuit Expired - Lifetime JPH0727694Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1987137073U JPH0727694Y2 (en) 1987-09-08 1987-09-08 Variable delay circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1987137073U JPH0727694Y2 (en) 1987-09-08 1987-09-08 Variable delay circuit

Publications (2)

Publication Number Publication Date
JPS6442625U true JPS6442625U (en) 1989-03-14
JPH0727694Y2 JPH0727694Y2 (en) 1995-06-21

Family

ID=31398170

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1987137073U Expired - Lifetime JPH0727694Y2 (en) 1987-09-08 1987-09-08 Variable delay circuit

Country Status (1)

Country Link
JP (1) JPH0727694Y2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06185246A (en) * 1992-09-18 1994-07-05 Nisshin Kensetsu Kogyo Kk Temporary perforated tent

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6043917A (en) * 1983-08-22 1985-03-08 Fujitsu Ltd Clock phase adjusting circuit
JPS6068714A (en) * 1983-09-26 1985-04-19 Hitachi Ltd Delay circuit

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6043917A (en) * 1983-08-22 1985-03-08 Fujitsu Ltd Clock phase adjusting circuit
JPS6068714A (en) * 1983-09-26 1985-04-19 Hitachi Ltd Delay circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06185246A (en) * 1992-09-18 1994-07-05 Nisshin Kensetsu Kogyo Kk Temporary perforated tent

Also Published As

Publication number Publication date
JPH0727694Y2 (en) 1995-06-21

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