JPS63181074U - - Google Patents
Info
- Publication number
- JPS63181074U JPS63181074U JP7022287U JP7022287U JPS63181074U JP S63181074 U JPS63181074 U JP S63181074U JP 7022287 U JP7022287 U JP 7022287U JP 7022287 U JP7022287 U JP 7022287U JP S63181074 U JPS63181074 U JP S63181074U
- Authority
- JP
- Japan
- Prior art keywords
- output
- detector
- reference voltage
- envelope detector
- envelope
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 2
- 238000001514 detection method Methods 0.000 description 1
Landscapes
- Television Signal Processing For Recording (AREA)
Description
第１図は本考案の一実施例を示すブロツク図、
第２図は従来技術の実施例を示すブロツク図であ
る。
１，１０：ＲＦ信号、２，１２：エンベロープ
検波器、３：積分器、４：ボリユーム、５，６，
１４：コンバレータ、７，１３：基準電圧発生器
、８：論理ＮＯＲ回路、９，１５：ドロツプアウ
ト検出信号、１１：ＡＧＣ回路。
FIG. 1 is a block diagram showing an embodiment of the present invention.
FIG. 2 is a block diagram showing an embodiment of the prior art. 1, 10: RF signal, 2, 12: envelope detector, 3: integrator, 4: volume, 5, 6,
14: Converter, 7, 13: Reference voltage generator, 8: Logic NOR circuit, 9, 15: Dropout detection signal, 11: AGC circuit.
Claims (1)
て、ＶＴＲの再生ＲＦ信号をエンベロープ検波す
るエンベロープ検波器と、再生ＲＦ信号レベルに
応じて変化する前記エンベロープ検波器の出力の
直流成分を検出し、かつ、時定数をドロツプアウ
ト等の瞬間的なレベル変化に追従しないように設
定した積分器と、前記積分器出力をしきい値電圧
とし、前記エンベロープ検波器の出力を入力とす
る第１のコンパレータと、基準電圧発生器と、こ
の基準電圧発生器の出力基準電圧をしきい値電圧
とし、前記エンベロープ検波器の出力を入力とす
る第２のコンパレータと、前記第１、第２のコン
パレータの出力を入力とする論理和または論理積
回路とから構成されたドロツプアウト検出器。 A dropout detector used in a VTR includes an envelope detector that envelope-detects the reproduced RF signal of the VTR, and a DC component of the output of the envelope detector that changes depending on the level of the reproduced RF signal, and a time constant. an integrator configured not to follow instantaneous level changes such as dropouts; a first comparator that uses the integrator output as a threshold voltage and receives the output of the envelope detector as an input; and a reference voltage generator. and a second comparator which has the output reference voltage of this reference voltage generator as a threshold voltage and which has the output of the envelope detector as an input, and a logical sum which has the outputs of the first and second comparators as inputs. or a dropout detector consisting of an AND circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7022287U JPS63181074U (en) | 1987-05-13 | 1987-05-13 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7022287U JPS63181074U (en) | 1987-05-13 | 1987-05-13 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63181074U true JPS63181074U (en) | 1988-11-22 |
Family
ID=30911662
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7022287U Pending JPS63181074U (en) | 1987-05-13 | 1987-05-13 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63181074U (en) |
-
1987
- 1987-05-13 JP JP7022287U patent/JPS63181074U/ja active Pending
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