JPS63136427U - - Google Patents
Info
- Publication number
- JPS63136427U JPS63136427U JP2828587U JP2828587U JPS63136427U JP S63136427 U JPS63136427 U JP S63136427U JP 2828587 U JP2828587 U JP 2828587U JP 2828587 U JP2828587 U JP 2828587U JP S63136427 U JPS63136427 U JP S63136427U
- Authority
- JP
- Japan
- Prior art keywords
- pulse signal
- inverting amplifier
- amplifier circuit
- input
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000006243 chemical reaction Methods 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 2
Description
第１図は、本考案によるパルス信号極性変換回
路の一実施例を示すブロツク図、第２図は、第１
図に示す回路の動作を説明する波形図、第３図は
、第１図に示す回路の動作を説明する波形図であ
る。
１……入力端子、２……コンデンサー、３……
コンデンサー、８……インバーター、９……イン
バーター、１２……イクスクルーシブオア回路、
１３……出力端子。
FIG. 1 is a block diagram showing an embodiment of a pulse signal polarity conversion circuit according to the present invention, and FIG.
3 is a waveform diagram explaining the operation of the circuit shown in FIG. 1. FIG. 3 is a waveform diagram explaining the operation of the circuit shown in FIG. 1...Input terminal, 2...Capacitor, 3...
Capacitor, 8... Inverter, 9... Inverter, 12... Exclusive OR circuit,
13...Output terminal.
Claims (1)
入力のときはハイレベルのパルス信号を出力する
ようにバイアスされた第１の反転増幅回路と、前
記入力パルス信号の交流成分を反転増幅し無信号
入力のときはローレベルのパルス信号を出力する
ようにバイアスされた第２の反転増幅回路と、前
記第１の反転増幅回路と前記第２の反転増幅回路
の２つの出力パルスのイクスクルーシブオアを出
力するイクスクルーシブオア回路とを有するパル
ス信号極性変換回路。 A first inverting amplifier circuit biased to invert and amplify the alternating current component of the input pulse signal and output a high-level pulse signal when there is no signal input; a second inverting amplifier circuit biased to output a low-level pulse signal when input, and an exclusive OR of the two output pulses of the first inverting amplifier circuit and the second inverting amplifier circuit; A pulse signal polarity conversion circuit having an exclusive OR circuit that outputs.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2828587U JPS63136427U (en) | 1987-02-26 | 1987-02-26 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2828587U JPS63136427U (en) | 1987-02-26 | 1987-02-26 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63136427U true JPS63136427U (en) | 1988-09-07 |
Family
ID=30831105
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2828587U Pending JPS63136427U (en) | 1987-02-26 | 1987-02-26 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63136427U (en) |
-
1987
- 1987-02-26 JP JP2828587U patent/JPS63136427U/ja active Pending
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