JPS5956843U - Pulse interval equalization circuit - Google Patents
Pulse interval equalization circuitInfo
- Publication number
- JPS5956843U JPS5956843U JP14981382U JP14981382U JPS5956843U JP S5956843 U JPS5956843 U JP S5956843U JP 14981382 U JP14981382 U JP 14981382U JP 14981382 U JP14981382 U JP 14981382U JP S5956843 U JPS5956843 U JP S5956843U
- Authority
- JP
- Japan
- Prior art keywords
- frequency
- output
- pulse train
- pulse interval
- equalization circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)
- Analogue/Digital Conversion (AREA)
- Signal Processing For Digital Recording And Reproducing (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
図面は本考案によるパルス間隔均等化回路の一実施例を
示す回路図である。
１・・・周波数引算回路、４，５・・・Ｄ／Ａ変換器、
６・・・演算増巾器、７・・・電圧／周波数変換器。The drawing is a circuit diagram showing an embodiment of a pulse interval equalization circuit according to the present invention. 1... Frequency subtraction circuit, 4, 5... D/A converter,
6... operational amplifier, 7... voltage/frequency converter.
Claims (1)
る周波数引算回路と、上記周波数差をそ□ の極
性を含むアナログ電圧に変換するＤ／Ａ変換器と、上記
Ｄ／Ａ変換差の出力電圧を積分する積分回路と、上記積
分回路の出力電圧を等間隔のパルス列に変換する電圧／
周波数変換回路を備え、上記電圧／周波数変換回路の出
力を出力パルス列として出力すると共に上記周波数引算
回路に出力パルス列として入力するようにしたパルス間
隔均等化回路。A frequency subtraction circuit that calculates the difference in average frequency between the input pulse train and the output pulse train, a D/A converter that converts the frequency difference into an analog voltage including the polarity, and an output voltage of the D/A conversion difference. and a voltage /
A pulse interval equalization circuit comprising a frequency conversion circuit, and configured to output the output of the voltage/frequency conversion circuit as an output pulse train and input it to the frequency subtraction circuit as an output pulse train.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14981382U JPS5956843U (en) | 1982-10-04 | 1982-10-04 | Pulse interval equalization circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14981382U JPS5956843U (en) | 1982-10-04 | 1982-10-04 | Pulse interval equalization circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5956843U true JPS5956843U (en) | 1984-04-13 |
Family
ID=30332454
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14981382U Pending JPS5956843U (en) | 1982-10-04 | 1982-10-04 | Pulse interval equalization circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5956843U (en) |
-
1982
- 1982-10-04 JP JP14981382U patent/JPS5956843U/en active Pending
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