JPS58138141U - Analog input capture device - Google Patents
Analog input capture deviceInfo
- Publication number
- JPS58138141U JPS58138141U JP3389882U JP3389882U JPS58138141U JP S58138141 U JPS58138141 U JP S58138141U JP 3389882 U JP3389882 U JP 3389882U JP 3389882 U JP3389882 U JP 3389882U JP S58138141 U JPS58138141 U JP S58138141U
- Authority
- JP
- Japan
- Prior art keywords
- analog input
- capture device
- input capture
- amplifier
- voltage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Analogue/Digital Conversion (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は従来技術のブロック図、第２図は一般的なアナ
ログ入力の変化図、第３閣は本考案のブロック図、第４
図は本考案の概略ソフトウェアブロック図、第５図は本
考案の概略ソフトウェアブロック図である。
１．１７・・・プロセス入力データ、２．１２・・・増
幅器、３．２０・・・ゲイン、４，２１・・・増幅器の
出力電圧、５，１３・・・Ａ／Ｄ変換器、６，２３・・
・Ａ／Ｄ変換値、７，１４・・・演算装置、８・・・工
学値、１８・・・前回プロセス入力データ、１９・・・
偏差値、１５・・・Ｄ／Ａ変換値、１６・・・電圧ホー
ルド回路、２４・・・今回プロセス入力データに対応す
るディジット値、３１〜３４・・・ソフトウェアの処理
。Figure 1 is a block diagram of the conventional technology, Figure 2 is a diagram of changes in general analog input, Figure 3 is a block diagram of the present invention, and Figure 4 is a block diagram of the present invention.
The figure is a schematic software block diagram of the present invention, and FIG. 5 is a schematic software block diagram of the present invention. 1.17... Process input data, 2.12... Amplifier, 3.20... Gain, 4, 21... Output voltage of amplifier, 5, 13... A/D converter, 6 ,23...
・A/D conversion value, 7, 14... Arithmetic device, 8... Engineering value, 18... Previous process input data, 19...
Deviation value, 15... D/A conversion value, 16... Voltage hold circuit, 24... Digit value corresponding to current process input data, 31 to 34... Software processing.
Claims (1)
化するＡ／Ｄ変換器、前記増幅器のゲインを指定する演
算装置からなる装置において、前記演算装置から与える
電圧と入力電圧との差分を前記増幅器に与えることを特
徴とするアナログ入力取込み装置。In a device comprising an amplifier for analog input voltage, an A/D converter for digitizing the amplified voltage, and an arithmetic device for specifying the gain of the amplifier, the difference between the voltage applied from the arithmetic device and the input voltage is sent to the amplifier. An analog input acquisition device characterized in that:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3389882U JPS58138141U (en) | 1982-03-12 | 1982-03-12 | Analog input capture device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3389882U JPS58138141U (en) | 1982-03-12 | 1982-03-12 | Analog input capture device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS58138141U true JPS58138141U (en) | 1983-09-17 |
Family
ID=30045423
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3389882U Pending JPS58138141U (en) | 1982-03-12 | 1982-03-12 | Analog input capture device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58138141U (en) |
-
1982
- 1982-03-12 JP JP3389882U patent/JPS58138141U/en active Pending
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