JPS6186900U - - Google Patents
Info
- Publication number
- JPS6186900U JPS6186900U JP17107884U JP17107884U JPS6186900U JP S6186900 U JPS6186900 U JP S6186900U JP 17107884 U JP17107884 U JP 17107884U JP 17107884 U JP17107884 U JP 17107884U JP S6186900 U JPS6186900 U JP S6186900U
- Authority
- JP
- Japan
- Prior art keywords
- hold
- input signal
- hold capacitor
- output
- terminal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000003990 capacitor Substances 0.000 claims description 5
- 238000001514 detection method Methods 0.000 claims description 4
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Measurement Of Current Or Voltage (AREA)
Description
第１図は本考案に係るピークホールド回路の一
実施例を示すブロツク図、第２図は第１図に示し
たピークホールド回路をより詳細に示す回路構成
図、第３図は従来のピークホールド回路を示す回
路構成図。
２…差動増幅器、４…ホールドコンデンサ、６
…バツフア増幅器、８…インパルス雑音検出回路
、９…可変電流源。
Fig. 1 is a block diagram showing an embodiment of the peak hold circuit according to the present invention, Fig. 2 is a circuit configuration diagram showing the peak hold circuit shown in Fig. 1 in more detail, and Fig. 3 is a conventional peak hold circuit. A circuit configuration diagram showing a circuit. 2...Differential amplifier, 4...Hold capacitor, 6
...Buffer amplifier, 8. Impulse noise detection circuit, 9. Variable current source.
Claims (1)
に入力信号およびピークホールド出力が供給され
る差動増幅器と、この差動増幅器の出力電圧を保
持するホールドコンデンサと、このホールドコン
デンサの端子電圧の供給を受け前記ピークホール
ド出力電圧を出力するバツフア増幅器と、前記入
力信号の供給を受け、この入力信号中のインパル
ス雑音を検出する雑音検出手段と、前記ホールド
コンデンサに並列接続され前記雑音検出手段の出
力する検出出力に応じて前記ホールドコンデンサ
の充電電荷を放電する可変電流源とを有すること
を特徴とするピークホールド回路。 A differential amplifier has a non-inverting input terminal and an inverting input terminal each supplied with an input signal and a peak hold output, a hold capacitor that holds the output voltage of this differential amplifier, and a terminal voltage of this hold capacitor that is supplied with the terminal voltage. a buffer amplifier that outputs the peak hold output voltage; a noise detection means that receives the input signal and detects impulse noise in the input signal; and a detection circuit that is connected in parallel to the hold capacitor and outputs from the noise detection means. A peak hold circuit comprising: a variable current source that discharges the charge in the hold capacitor according to an output.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17107884U JPS6186900U (en) | 1984-11-13 | 1984-11-13 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17107884U JPS6186900U (en) | 1984-11-13 | 1984-11-13 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6186900U true JPS6186900U (en) | 1986-06-06 |
Family
ID=30728779
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17107884U Pending JPS6186900U (en) | 1984-11-13 | 1984-11-13 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6186900U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03295472A (en) * | 1990-04-13 | 1991-12-26 | Rohm Co Ltd | Peak holding circuit |
| JP4754704B2 (en) * | 2001-03-27 | 2011-08-24 | 島田理化工業株式会社 | Automatic sample hold device and pulse modulation high frequency signal generator |
-
1984
- 1984-11-13 JP JP17107884U patent/JPS6186900U/ja active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03295472A (en) * | 1990-04-13 | 1991-12-26 | Rohm Co Ltd | Peak holding circuit |
| JP4754704B2 (en) * | 2001-03-27 | 2011-08-24 | 島田理化工業株式会社 | Automatic sample hold device and pulse modulation high frequency signal generator |
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