JPH01147518U - - Google Patents
Info
- Publication number
- JPH01147518U JPH01147518U JP4403388U JP4403388U JPH01147518U JP H01147518 U JPH01147518 U JP H01147518U JP 4403388 U JP4403388 U JP 4403388U JP 4403388 U JP4403388 U JP 4403388U JP H01147518 U JPH01147518 U JP H01147518U
- Authority
- JP
- Japan
- Prior art keywords
- switch
- capacitor
- clock signal
- voltage source
- operational amplifier
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000003990 capacitor Substances 0.000 claims description 7
- 238000001514 detection method Methods 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 5
Landscapes
- Circuits Of Receivers In General (AREA)
- Television Signal Processing For Recording (AREA)
Description
第1図は本考案の一実施例に係るFM検波回路
の回路図、第2図は前記FM検波回路を含む復調
回路の構成を示すブロツク図、第3図は演算増幅
器26の出力レベルを示す図、第4図は従来の復
調回路の構成を示すブロツク図、第5図はトリガ
回路3の回路図、第6図は単安定マルチバイブレ
ータ4の回路図である。
21…定電圧源、22…第1のキヤパシタ、2
3…第1のスイツチ、24…第2のスイツチ、2
5…第3のスイツチ、26…演算増幅器、27…
第4のスイツチ、28…第5のスイツチ、29…
第2のキヤパシタ。
FIG. 1 is a circuit diagram of an FM detection circuit according to an embodiment of the present invention, FIG. 2 is a block diagram showing the configuration of a demodulation circuit including the FM detection circuit, and FIG. 3 shows the output level of the operational amplifier 26. 4 is a block diagram showing the configuration of a conventional demodulation circuit, FIG. 5 is a circuit diagram of the trigger circuit 3, and FIG. 6 is a circuit diagram of the monostable multivibrator 4. 21... constant voltage source, 22... first capacitor, 2
3...first switch, 24...second switch, 2
5...Third switch, 26...Operation amplifier, 27...
Fourth switch, 28...Fifth switch, 29...
Second capacitor.
Claims (1)
間にクロツク信号によつてオンオフする第1のス
イツチを設け、 前記定電圧源の他端と前記第1のキヤパシタの
一端との間に前記クロツク信号を反転した信号で
オンオフする第2のスイツチを設け、 前記定電圧源の他端と前記第1のキヤパシタの
他端との間に前記クロツク信号によつてオンオフ
する第3のスイツチを設け、 前記定電圧源の他端と演算増幅器の非反転入力
端子とを接続し、 前記第1のキヤパシタの他端と前記演算増幅器
の反転入力端子との間に前記クロツク信号を反転
した信号でオンオフする第4のスイツチを設け、 前記演算増幅器の反転入力端子と出力端子との
間に互いに並列接続された第5のスイツチと第2
のキヤパシタとを設けることを特徴とするFM検
波回路。[Claims for Utility Model Registration] A first switch that is turned on and off by a clock signal is provided between one end of the constant voltage source and one end of the first capacitor; A second switch is provided between one end of the capacitor and turned on and off by an inverted signal of the clock signal, and a second switch is provided between the other end of the constant voltage source and the other end of the first capacitor by the clock signal. A third switch that turns on and off is provided, the other end of the constant voltage source is connected to the non-inverting input terminal of the operational amplifier, and the third switch is connected between the other end of the first capacitor and the inverting input terminal of the operational amplifier. A fourth switch is provided that is turned on and off by an inverted clock signal, and a fifth switch and a second switch are connected in parallel to each other between the inverting input terminal and the output terminal of the operational amplifier.
An FM detection circuit comprising: a capacitor.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4403388U JPH01147518U (en) | 1988-03-31 | 1988-03-31 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4403388U JPH01147518U (en) | 1988-03-31 | 1988-03-31 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH01147518U true JPH01147518U (en) | 1989-10-12 |
Family
ID=31270410
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP4403388U Pending JPH01147518U (en) | 1988-03-31 | 1988-03-31 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH01147518U (en) |
-
1988
- 1988-03-31 JP JP4403388U patent/JPH01147518U/ja active Pending
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