JPS6340899U - - Google Patents
Info
- Publication number
- JPS6340899U JPS6340899U JP13491686U JP13491686U JPS6340899U JP S6340899 U JPS6340899 U JP S6340899U JP 13491686 U JP13491686 U JP 13491686U JP 13491686 U JP13491686 U JP 13491686U JP S6340899 U JPS6340899 U JP S6340899U
- Authority
- JP
- Japan
- Prior art keywords
- switch
- operational amplifier
- inverting input
- input terminal
- terminal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000003990 capacitor Substances 0.000 claims description 5
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Filters That Use Time-Delay Elements (AREA)
- Amplifiers (AREA)
Description
第１図は本考案の実施例を示す略式回路図、第
２図は従来例を示す略式回路図である。
１……入力信号端子、Ｓ１〜Ｓ４……第１ない
し第４のスイツチ、Ｃ１……第１のコンデンサ、
２……演算増幅器、Ｃ２……第２のコンデンサ、
３……出力端子。
FIG. 1 is a schematic circuit diagram showing an embodiment of the present invention, and FIG. 2 is a schematic circuit diagram showing a conventional example. 1...Input signal terminal, S1 to S4 ...first to fourth switch, C1 ...first capacitor,
2... operational amplifier, C 2 ... second capacitor,
3...Output terminal.
Claims (1)
基準電位に接続された第１のコンデンサ及び演算
増幅器の非反転入力端子に接続すると共に第２の
スイツチと第２のコンデンサの直列回路を介して
上記演算増幅器の反転入力端子に接続し、 上記演算増幅器の出力端子を第３のスイツチを
介して上記反転入力端子に接続すると共に第４の
スイツチを介して上記第２のスイツチと第２のコ
ンデンサの接続点に接続し、 上記第１ないし第３のスイツチをサンプル期間
にオンさせ、上記第４のスイツチをホールド期間
にオンさせるようにしたサンプルホールド回路。[Claims for Utility Model Registration] An input signal terminal is connected to a non-inverting input terminal of an operational amplifier and a first capacitor whose other end is connected to a reference potential via a first switch, and a second switch and a second switch are connected to each other. The output terminal of the operational amplifier is connected to the inverting input terminal through a third switch, and the output terminal is connected through a fourth switch to the inverting input terminal of the operational amplifier through a series circuit of two capacitors. A sample and hold circuit connected to a connection point between a second switch and a second capacitor, and configured to turn on the first to third switches during the sample period and turn on the fourth switch during the hold period.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13491686U JPS6340899U (en) | 1986-09-03 | 1986-09-03 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13491686U JPS6340899U (en) | 1986-09-03 | 1986-09-03 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6340899U true JPS6340899U (en) | 1988-03-17 |
Family
ID=31036609
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13491686U Pending JPS6340899U (en) | 1986-09-03 | 1986-09-03 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6340899U (en) |
-
1986
- 1986-09-03 JP JP13491686U patent/JPS6340899U/ja active Pending