JPH0242299U

JPH0242299U -

Info

Publication number: JPH0242299U
Application number: JP11987788U
Authority: JP
Priority date: 1988-09-14
Filing date: 1988-09-14
Publication date: 1990-03-23

Description

[Brief explanation of the drawing]

第１図は本考案に係るピークホールド回路の実
施例を示す図、第２図は第１図のタイムチヤート
、第３図は従来例を示す図、第４図は第３図のタ
イムチヤートである。１……第１の初段ホールド回路、２……第１の
次段ホールド回路、３……反転器、１１……第２
の初段ホールド回路、２２……第２の次段ホール
ド回路。 Fig. 1 is a diagram showing an embodiment of the peak hold circuit according to the present invention, Fig. 2 is a time chart of Fig. 1, Fig. 3 is a diagram showing a conventional example, and Fig. 4 is a time chart of Fig. 3. be. DESCRIPTION OF SYMBOLS 1...First initial stage hold circuit, 2...First next stage hold circuit, 3...Inverter, 11...Second stage hold circuit
1st stage hold circuit, 22... second next stage hold circuit.

Claims

[Claims for Utility Model Registration] Rectifying means for extracting the positive waveform of an input signal, a capacitor C1 charged to the positive peak voltage of the rectifying means,
Buffer amplifier U2 that receives this capacitor voltage
and a first next-stage hold circuit which receives the output of the buffer amplifier and has the same configuration as the first first-stage hold circuit except that it includes a capacitor C2 having a larger capacity than the capacitor C1. an inverter that inverts the polarity of the input signal; a second first-stage hold circuit that has the same configuration as the first first-stage hold circuit that introduces the output signal of the inverter; and a second first-stage hold circuit that receives the output of the second first-stage hold circuit. , a second next-stage hold circuit having the same configuration as the first next-stage hold circuit, and a peak hold circuit.