JPS58161334U

JPS58161334U - monostable multivibrator

Info

Publication number: JPS58161334U
Application number: JP1982056388U
Authority: JP
Inventors: 高橋　守郎; 正人田辺
Original assignee: 株式会社東芝
Priority date: 1982-04-20
Filing date: 1982-04-20
Publication date: 1983-10-27

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Brief explanation of drawings]

第１図は従来の単安定マルチバイブレークのブロック図
、第２図Ａ〜Ｅは第１図のタイムチャート、第３図は本
考案になる単安定マルチバイブレータの論理回路、第４
図Ａ〜には第３図のタイムチャートである。　、図中符号８はＤフリップフロップ、５は第１の論理回路
、６は第２の論理回路、７はアンド回路、９は遅延形単
安定マルチバイブレータ、１０は時定数制御回路、１１
は基準電圧切換回路、１２は差動増幅器、１３は位相変
換増幅器、Ａ、　Ｃ，Ｘはピン、Ｃ１はコンデンサであ
る。Fig. 1 is a block diagram of a conventional monostable multivibrator, Fig. 2 A to E are time charts of Fig. 1, Fig. 3 is a logic circuit of a monostable multivibrator according to the present invention, and Fig. 4 is a block diagram of a conventional monostable multivibrator.
Figures A~ are time charts of Figure 3. , In the figure, 8 is a D flip-flop, 5 is a first logic circuit, 6 is a second logic circuit, 7 is an AND circuit, 9 is a delayed monostable multivibrator, 10 is a time constant control circuit, 11
1 is a reference voltage switching circuit, 12 is a differential amplifier, 13 is a phase conversion amplifier, A, C, and X are pins, and C1 is a capacitor.

Claims

[Scope of utility model registration request]

A capacitor that is charged at the falling edge of the trigger pulse and discharged at the rising edge is connected to one input terminal, and a reference potential switching means for switching the first reference potential to the second reference potential at the falling edge of the trigger pulse is connected to the other input terminal. In a monostable multi-bibreak, which has a differential amplifier connected to the input terminal of the differential amplifier and becomes a metastable state depending on the charging/discharging time of the capacitor, the input square pulse is used as the data input, and the input terminal of the differential amplifier is connected to the input terminal of the differential amplifier. a D flip-flop whose clock input is an output in a quasi-stable state; a first logic circuit which becomes negative logic at the rising edge of the square pulse; and returns to positive logic in accordance with the operation of the D flip-flop; and a second logic circuit which becomes a negative logic at a time and returns to a positive logic in accordance with the operation of the aforementioned aD flip-flop, and is configured to generate the trigger pulse at the rising and falling points of the square pulse. Characteristic monostable multivibrator.