JPS61179830U - - Google Patents

Info

Publication number
JPS61179830U
JPS61179830U JP6267885U JP6267885U JPS61179830U JP S61179830 U JPS61179830 U JP S61179830U JP 6267885 U JP6267885 U JP 6267885U JP 6267885 U JP6267885 U JP 6267885U JP S61179830 U JPS61179830 U JP S61179830U
Authority
JP
Japan
Prior art keywords
flop
flip
stage
input terminal
terminal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP6267885U
Other languages
Japanese (ja)
Other versions
JPH0352037Y2 (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1985062678U priority Critical patent/JPH0352037Y2/ja
Publication of JPS61179830U publication Critical patent/JPS61179830U/ja
Application granted granted Critical
Publication of JPH0352037Y2 publication Critical patent/JPH0352037Y2/ja
Expired legal-status Critical Current

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  • Manipulation Of Pulses (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本考案に係る回路の構成ブロツク図、
第２図は動作の一例を示す動作波形図である。 Ｆ１……第１段目Ｄフリツプフロツプ、Ｆ２…
…第２段目Ｄフリツプフロツプ、Ｓ１……シフト
レジスタ。 Figure 1 is a block diagram of the circuit structure according to the present invention.
FIG. 2 is an operation waveform diagram showing an example of the operation. F1...1st stage D flip-flop, F2...
...Second stage D flip-flop, S1...Shift register.

Claims (1)

【実用新案登録請求の範囲】 Ｄ入力端子にハイレベル電圧が印加され、リセ
ツト端子に入力信号が印加され、クロツク入力端
子に所定周期のクロツク信号が印加される第１段
目のＤフリツプフロツプと、Ｄ入力端子に前記第
１段目のＤフリツプフロツプのＱ出力信号が印加
され、リセツト端子にハイレベル電圧が印加され
、クロツク入力端子に前記クロツク信号が印加さ
れる第２段目のＤフリツプフロツプとを備え、 前記第２段目のＤフリツプフロツプの出力端
子から出力信号を得るようにしたリトリガラブル
モノマルチ。[Claims for Utility Model Registration] A first-stage D flip-flop to which a high-level voltage is applied to the D input terminal, an input signal is applied to the reset terminal, and a clock signal of a predetermined period is applied to the clock input terminal; The Q output signal of the first stage D flip-flop is applied to the D input terminal, the high level voltage is applied to the reset terminal, and the second stage D flip-flop is applied to the clock input terminal. A retriggerable monomulti, wherein an output signal is obtained from an output terminal of the second stage D flip-flop.
JP1985062678U 1985-04-26 1985-04-26 Expired JPH0352037Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1985062678U JPH0352037Y2 (en) 1985-04-26 1985-04-26

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1985062678U JPH0352037Y2 (en) 1985-04-26 1985-04-26

Publications (2)

Publication Number Publication Date
JPS61179830U true JPS61179830U (en) 1986-11-10
JPH0352037Y2 JPH0352037Y2 (en) 1991-11-11

Family

ID=30592118

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1985062678U Expired JPH0352037Y2 (en) 1985-04-26 1985-04-26

Country Status (1)

Country Link
JP (1) JPH0352037Y2 (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5427549A (en) * 1977-07-29 1979-03-01 American Cyanamid Co Production of 22aminoo11 naphthalenesulphonic acid
JPS5910025A (en) * 1982-07-07 1984-01-19 Fujitsu Ltd Automatic frequency controlling system

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5427549A (en) * 1977-07-29 1979-03-01 American Cyanamid Co Production of 22aminoo11 naphthalenesulphonic acid
JPS5910025A (en) * 1982-07-07 1984-01-19 Fujitsu Ltd Automatic frequency controlling system

Also Published As

Publication number Publication date
JPH0352037Y2 (en) 1991-11-11

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