JPS6144940U - ring counter circuit - Google Patents
ring counter circuitInfo
- Publication number
- JPS6144940U JPS6144940U JP13008584U JP13008584U JPS6144940U JP S6144940 U JPS6144940 U JP S6144940U JP 13008584 U JP13008584 U JP 13008584U JP 13008584 U JP13008584 U JP 13008584U JP S6144940 U JPS6144940 U JP S6144940U
- Authority
- JP
- Japan
- Prior art keywords
- flop
- output
- input
- type flip
- flip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Television Signal Processing For Recording (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は従来例を示すブロック図、第２図は第１図の動
作を示すタイミング図、第３図は本考案の一実施例を示
すブロック図、第４図は第３図の動作を示すタイミング
図である。
ＦＦｌ〜５・・・・・・Ｄ型フリップフロップ、ＩＤ入
力信号発生回路部、２・・・・・・２人力ＯＲ回路、２
１・・・・・・ＯＲ回路。FIG. 1 is a block diagram showing a conventional example, FIG. 2 is a timing diagram showing the operation of FIG. 1, FIG. 3 is a block diagram showing an embodiment of the present invention, and FIG. 4 is a block diagram showing the operation of FIG. 3. FIG. FFl~5...D-type flip-flop, ID input signal generation circuit section, 2...2 manual OR circuit, 2
1...OR circuit.
Claims (1)
フリツプフロツプ群と、前記Ｄ型フリツプフロツプ群の
ＲＳ入力に共通のリセット信号を供給し前記Ｄ型フリツ
プフロツプ群のＴ出力をＨとする手段と、前記Ｄ型フリ
ツプフロツプ群のうちの初段の第一のフリツプフロツプ
のＴ出力をＣＬＫ入力とし、ＬをＤ入力とし、前記リセ
ット信号をＭＳ入力と前記リモット信号によりＴ出力が
Ｈどなる第二のＤ型フリツプフロツプと、前記第二のＤ
型フリツプフロツプのＴ出力と前記Ｄ型フリツプフロツ
プ群のうちの最終段の第三のＤ型フリップフロツプのＴ
出力を入力とし、そのＯＲ出力を前記第一のフリツプフ
ロツプのＤ入力とするＯＲ回路と、前記Ｄ型フリップフ
ロップ群のＭＳ入力にＨを供給し、そのＴ出力がＨとな
ることを禁止し、第二のフリツプフロツプのＲＳ入力に
Ｈを供給し、そのＴ出力がＬとなることを禁止する手段
とを有することを特徴とするリングカウンタ回路。Means for supplying a common reset signal to a plurality of D-type flip-flop groups connected in series with the T output as the D-input of the next stage and the RS input of the D-type flip-flop group to set the T output of the D-type flip-flop group to H. The T output of the first flip-flop in the first stage of the D-type flip-flop group is used as the CLK input, the L is used as the D input, the reset signal is applied as the MS input, and the T output becomes H due to the remote signal. type flip-flop and said second D
The T output of the D-type flip-flop and the T output of the third D-type flip-flop in the final stage of the D-type flip-flop group.
an OR circuit which takes the output as an input and whose OR output is the D input of the first flip-flop, supplies H to the MS input of the D-type flip-flop group, and prohibits its T output from becoming H; A ring counter circuit comprising means for supplying H to the RS input of the second flip-flop and prohibiting its T output from becoming L.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13008584U JPS6144940U (en) | 1984-08-28 | 1984-08-28 | ring counter circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13008584U JPS6144940U (en) | 1984-08-28 | 1984-08-28 | ring counter circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6144940U true JPS6144940U (en) | 1986-03-25 |
Family
ID=30688696
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13008584U Pending JPS6144940U (en) | 1984-08-28 | 1984-08-28 | ring counter circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6144940U (en) |
-
1984
- 1984-08-28 JP JP13008584U patent/JPS6144940U/en active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPS6144940U (en) | ring counter circuit | |
| JPS61179830U (en) | ||
| JPS607156U (en) | mass marker circuit | |
| JPS60103941U (en) | D/A converter device | |
| JPS6034615U (en) | Stabilized voltage circuit | |
| JPS5816564U (en) | hysteresis circuit | |
| JPS618301U (en) | Analog tracking circuit | |
| JPS60184334U (en) | pulse counter | |
| JPS5811332U (en) | Waveform shaping circuit | |
| JPS5857918U (en) | Highest point holding circuit | |
| JPS60114443U (en) | Analog-digital converter | |
| JPS5933336U (en) | Simple digital to analog converter | |
| JPS5840941U (en) | analog to digital converter | |
| JPS6126324U (en) | Pulse width modulation control signal generator | |
| JPS5850556U (en) | Binarization circuit | |
| JPS60124134U (en) | signal shaping circuit | |
| JPS60127033U (en) | Logic circuit output circuit | |
| JPS5837229U (en) | logic circuit | |
| JPS60173080U (en) | Signal discrimination circuit | |
| JPS5854131U (en) | Comparator input circuit | |
| JPS6133456U (en) | Photocoupler element | |
| JPS586435U (en) | Multiphase generation circuit | |
| JPS615028U (en) | M series generator | |
| JPS59157335U (en) | Multiphase clock generation circuit | |
| JPS6239300U (en) |