JPS618301U - Analog tracking circuit - Google Patents
Analog tracking circuitInfo
- Publication number
- JPS618301U JPS618301U JP9331384U JP9331384U JPS618301U JP S618301 U JPS618301 U JP S618301U JP 9331384 U JP9331384 U JP 9331384U JP 9331384 U JP9331384 U JP 9331384U JP S618301 U JPS618301 U JP S618301U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- input
- analog
- output
- tracking circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は本考案実施例回路図。
第２図はその動作タイムチャート。
第３図は従来例回路図。第４図はその動作タイムチャー
ト。
ＣＴ−・・アツプダウンカウンタ、ＤＡ・・・デイジタ
ルアナログ変換回路、ＣＰ・・・比較回路。FIG. 1 is a circuit diagram of an embodiment of the present invention. Figure 2 is an operation time chart. FIG. 3 is a conventional circuit diagram. Figure 4 is an operation time chart. CT--up/down counter, DA--digital-to-analog conversion circuit, CP--comparison circuit.
Claims (1)
れ、クロック信号を計数するアツプダウンカウンタと、 このカウンタの並列出力を入力とするデイジタルアナロ
グ変換回路と、 このデイジタルアナログ変換回路のアナログ出力が接続
された出力端子と、 このアナログ出力を上記比較回路の他方の入力に接続す
る帰還回路と、 を備えたアナログ追従回路において、 上記クロック信号を入力としその出力が上記比較のいず
れか一方の入力信号に重畳されるように接続された微分
回路を備えたことを特徴とするアナログ追従回路。[Claims for Utility Model Registration] A DC signal input terminal, a comparator circuit with one input connected to this input terminal, and an up-down circuit whose output is connected to an up-down switching input to count clock signals. a counter; a digital-to-analog conversion circuit that receives the parallel outputs of this counter; an output terminal to which the analog output of this digital-to-analog conversion circuit is connected; and a feedback circuit that connects this analog output to the other input of the comparison circuit. and an analog follow-up circuit comprising: a differentiator circuit connected to receive the clock signal as input and whose output is superimposed on one of the input signals for comparison. .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9331384U JPS618301U (en) | 1984-06-21 | 1984-06-21 | Analog tracking circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9331384U JPS618301U (en) | 1984-06-21 | 1984-06-21 | Analog tracking circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS618301U true JPS618301U (en) | 1986-01-18 |
| JPH0353281Y2 JPH0353281Y2 (en) | 1991-11-21 |
Family
ID=30650880
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9331384U Granted JPS618301U (en) | 1984-06-21 | 1984-06-21 | Analog tracking circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS618301U (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP2218055B1 (en) | 2007-11-14 | 2014-07-16 | Varcode Ltd. | A system and method for quality management utilizing barcode indicators |
| US8807422B2 (en) | 2012-10-22 | 2014-08-19 | Varcode Ltd. | Tamper-proof quality management barcode indicators |
-
1984
- 1984-06-21 JP JP9331384U patent/JPS618301U/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0353281Y2 (en) | 1991-11-21 |
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