JPS593632U - time delay circuit - Google Patents
time delay circuitInfo
- Publication number
- JPS593632U JPS593632U JP1982098520U JP9852082U JPS593632U JP S593632 U JPS593632 U JP S593632U JP 1982098520 U JP1982098520 U JP 1982098520U JP 9852082 U JP9852082 U JP 9852082U JP S593632 U JPS593632 U JP S593632U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- output
- time delay
- shot
- inputs
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Pulse Circuits (AREA)
- Electronic Switches (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第1図は従来の時間遅れ回路の回路図、第2図a、
bは同上の動作タイムチャート、第3図は本考案の一実
施例の回路図、第4図a −eは同上の動作タイムチャ
ート、第5図は同上のワンショット回路の回路図、第6
図は同上のクロックラッチ回路の回路図である。
1・・・ワンショット回路、2−・・クロックラッチ回
路、3・・・NOR回路。
第4図 −
第5図Figure 1 is a circuit diagram of a conventional time delay circuit, Figure 2a,
FIG. 3 is a circuit diagram of an embodiment of the present invention; FIGS. 4 a - e are operation time charts of the same as the above; FIG. 5 is a circuit diagram of the one-shot circuit of the same; FIG.
The figure is a circuit diagram of the clock latch circuit same as above. 1... One-shot circuit, 2-... Clock latch circuit, 3... NOR circuit. Figure 4 - Figure 5
Claims (1)
数で定まる巾の出力パルスを出力するワンシミツト回路
と、前記入力信号を入力端子に入力するとともに反転信
号をリセット端子に入力し且つ前記ワンショット回路の
出力をクロック端子に入力し前記ワンショット回路の出
力パルスの立上りで“L9tとなり入力信号の立上りで
“H゛となる出力を出すクロックラッチ回路と、前記ワ
ンショット回路の出力パルスとりdツクラッチ回路の出
力とを入力しワンショット回路の出力パルスの立上りで
“Httとなリフロックラッチ回路の出力の立上りでL
゛となる出力を出すNOR回路とにより成る時間遅れ回
路。a one-shot circuit that outputs an output pulse with a width determined by a CR time constant after a time delay caused by the circuit from the rising edge of an input signal; and a one-shot circuit that inputs the input signal to an input terminal and inputs an inverted signal to a reset terminal; a clock latch circuit that inputs the output of the one-shot circuit to a clock terminal and outputs an output that becomes "L9t" at the rising edge of the output pulse of the one-shot circuit and becomes "H" at the rising edge of the input signal; and a d-two clutch circuit that takes the output pulse of the one-shot circuit. The output of
A time delay circuit consisting of a NOR circuit and a NOR circuit that outputs an output.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1982098520U JPS593632U (en) | 1982-06-30 | 1982-06-30 | time delay circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1982098520U JPS593632U (en) | 1982-06-30 | 1982-06-30 | time delay circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS593632U true JPS593632U (en) | 1984-01-11 |
Family
ID=30233867
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1982098520U Pending JPS593632U (en) | 1982-06-30 | 1982-06-30 | time delay circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS593632U (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62236234A (en) * | 1986-04-08 | 1987-10-16 | Nec Corp | Broadcasting radio system |
-
1982
- 1982-06-30 JP JP1982098520U patent/JPS593632U/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62236234A (en) * | 1986-04-08 | 1987-10-16 | Nec Corp | Broadcasting radio system |
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