JPS6415400U - - Google Patents
Info
- Publication number
- JPS6415400U JPS6415400U JP10802387U JP10802387U JPS6415400U JP S6415400 U JPS6415400 U JP S6415400U JP 10802387 U JP10802387 U JP 10802387U JP 10802387 U JP10802387 U JP 10802387U JP S6415400 U JPS6415400 U JP S6415400U
- Authority
- JP
- Japan
- Prior art keywords
- diode
- diodes
- circuit
- series
- series circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000003990 capacitor Substances 0.000 claims description 4
- 230000000295 complement effect Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 4
Description
第１図は本考案に係るサンプル・ホールド回路
の一実施例の接続図、第２図は第１図回路の動作
を説明する為の図、第３図は従来のこの種の回路
の一例の接続図、第４図及び第５図は第３図回路
の動作を説明するための図である。
１…ダイオード・ブリツジ・ゲート、Ｃ…ホー
ルド用コンデンサ、Ｄ５〜Ｄ８…ダイオード、Ｃ
１…ゲート電位保持用コンデンサ。
Fig. 1 is a connection diagram of an embodiment of the sample-and-hold circuit according to the present invention, Fig. 2 is a diagram for explaining the operation of the circuit shown in Fig. 1, and Fig. 3 is an example of a conventional circuit of this type. The connection diagrams, FIGS. 4 and 5 are diagrams for explaining the operation of the circuit shown in FIG. 3. 1...Diode bridge gate, C...Hold capacitor, D5-D8...Diode, C
1...Capacitor for holding gate potential.
Claims (1)
で駆動されてオン、オフされるダイオード・ブリ
ツジ・ゲートの出力端子に入力端子より印加され
る信号をホールドするホールド用コンデンサを接
続するとともに、前記制御端子間にダイオード・
ブリツジ・ゲートのダイオードとは逆方向に一対
のダイオードを直列に接続してなるサンプル・ホ
ールド回路において、前記ダイオード直列回路に
並列にこのダイオード直列回路とは逆方向に一対
のダイオードを直列に接続してなる第２のダイオ
ード直列回路を設け、両ダイオード直列回路の中
点に前記ダイオード・ブリツジ・ゲートの電位を
保持するコンデンサを接続してなるサンプル・ホ
ールド回路。 A hold capacitor for holding the signal applied from the input terminal is connected to the output terminal of the diode bridge gate, which is turned on and off by being driven by complementary current pulses applied between the control terminals. A diode between
In a sample-and-hold circuit consisting of a pair of diodes connected in series in the opposite direction to the diodes of the bridge gate, a pair of diodes is connected in series in the opposite direction to the diode series circuit in parallel with the diode series circuit. A sample-and-hold circuit comprising: a second diode series circuit comprising a second diode series circuit; and a capacitor for holding the potential of the diode bridge gate connected to the midpoint of both diode series circuits.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10802387U JPS6415400U (en) | 1987-07-14 | 1987-07-14 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10802387U JPS6415400U (en) | 1987-07-14 | 1987-07-14 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6415400U true JPS6415400U (en) | 1989-01-26 |
Family
ID=31342967
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10802387U Pending JPS6415400U (en) | 1987-07-14 | 1987-07-14 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6415400U (en) |
-
1987
- 1987-07-14 JP JP10802387U patent/JPS6415400U/ja active Pending
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