JPS59127383U - switch circuit - Google Patents
switch circuitInfo
- Publication number
- JPS59127383U JPS59127383U JP1982983U JP1982983U JPS59127383U JP S59127383 U JPS59127383 U JP S59127383U JP 1982983 U JP1982983 U JP 1982983U JP 1982983 U JP1982983 U JP 1982983U JP S59127383 U JPS59127383 U JP S59127383U
- Authority
- JP
- Japan
- Prior art keywords
- transistors
- transistor
- turned
- output circuit
- current source
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Processing Of Color Television Signals (AREA)
- Electronic Switches (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図はこの考案を説明するための図、第２図はこの考
案の一例の接続図である。
Ｔ□〜Ｔ、は入力端子、Ｔ５は出力端子である。FIG. 1 is a diagram for explaining this invention, and FIG. 2 is a connection diagram of an example of this invention. T□ to T are input terminals, and T5 is an output terminal.
Claims (1)
のトランジスタを定電流源として第３及び第４のトラン
ジスタが差動接続され、上記第２のトランジスタを定電
流源として第５及び第６のトランジスタが差動接続され
、上記第３及び第６のトランジスタあコレクタと、上記
第４及び第５のトランジスタのコレクタとの少なくとも
一方が出力回路に接続され、上記出力回路にはその出力
をオンオフ制御する第７のトランジスタが接続され、上
記第３及び第６のトランジスタのベースがそれぞれ第１
及び第２の入力端子に接続され、上記第１及び第２の入
力端子の少なくとも一方にサブキャリア信号が供給され
ると共に、上記第１及び第２のトランジスタがオンまた
はオフとされ、かつ、上記第７のトランジスタがバース
トフラグパルスによりオンオフされるときには、上記出
力回路からバースト信号が取り出され、上記第１及び第
２の入力端子の一方及び他方に入力信号及び上記第７の
トランジスタをオフとするレベルが供給されると共に、
上記第１及び第２のトランジスタがオン及びオフとされ
るときには、上記出力回路から上記入力信号のバッファ
出力が取り出されるスイッチ回路。The first and second transistors are differentially connected, and the first transistor
The third and fourth transistors are differentially connected using the transistor as a constant current source, the fifth and sixth transistors are differentially connected using the second transistor as a constant current source, and the third and sixth transistors are differentially connected using the second transistor as a constant current source. At least one of the transistor A collector and the collectors of the fourth and fifth transistors is connected to an output circuit, a seventh transistor for controlling the output on and off is connected to the output circuit, and the third and fifth transistors are connected to each other. The bases of the 6 transistors are the first
and a second input terminal, a subcarrier signal is supplied to at least one of the first and second input terminals, and the first and second transistors are turned on or off, and the When the seventh transistor is turned on and off by the burst flag pulse, a burst signal is taken out from the output circuit, and an input signal is applied to one and the other of the first and second input terminals, and the seventh transistor is turned off. As the level is supplied,
A switch circuit from which a buffered output of the input signal is taken out from the output circuit when the first and second transistors are turned on and off.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1982983U JPS59127383U (en) | 1983-02-14 | 1983-02-14 | switch circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1982983U JPS59127383U (en) | 1983-02-14 | 1983-02-14 | switch circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59127383U true JPS59127383U (en) | 1984-08-27 |
Family
ID=30150965
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1982983U Pending JPS59127383U (en) | 1983-02-14 | 1983-02-14 | switch circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59127383U (en) |
-
1983
- 1983-02-14 JP JP1982983U patent/JPS59127383U/en active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPS59127383U (en) | switch circuit | |
| JPS5834433U (en) | AFT signal detection circuit | |
| JPS6040132U (en) | Phase switching circuit | |
| JPS59126314U (en) | power circuit | |
| JPS60158113U (en) | Level display device with volume position display | |
| JPS60153029U (en) | bidirectional transistor switch circuit | |
| JPS59189335U (en) | Auto clear circuit | |
| JPS5914419U (en) | Tuning circuit | |
| JPS5811330U (en) | Waveform shaping circuit | |
| JPS5920740U (en) | squelch circuit | |
| JPS6050541U (en) | Signal switching circuit | |
| JPS60172434U (en) | Malfunction prevention circuit at startup | |
| JPS591235U (en) | signal input circuit | |
| JPS59127367U (en) | clamp circuit | |
| JPS5866712U (en) | Muting circuit | |
| JPS58132410U (en) | rear equalizer circuit | |
| JPS60193715U (en) | Pulse polarity designation circuit | |
| JPS58164340U (en) | Signal switching circuit | |
| JPS59174611U (en) | Constant voltage power supply circuit | |
| JPS59125170U (en) | nonlinear circuit | |
| JPS59180383U (en) | Connection terminal with signal switching function | |
| JPS5984962U (en) | signal synthesis circuit | |
| JPS59162720U (en) | switch input circuit | |
| JPS59144916U (en) | Tone control circuit | |
| JPS6042096U (en) | Motor control circuit |