JPS645533U - - Google Patents
Info
- Publication number
- JPS645533U JPS645533U JP9822487U JP9822487U JPS645533U JP S645533 U JPS645533 U JP S645533U JP 9822487 U JP9822487 U JP 9822487U JP 9822487 U JP9822487 U JP 9822487U JP S645533 U JPS645533 U JP S645533U
- Authority
- JP
- Japan
- Prior art keywords
- resistor
- inverter
- input
- integrating circuit
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000003990 capacitor Substances 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 5
- 230000010354 integration Effects 0.000 description 1
Landscapes
- Manipulation Of Pulses (AREA)
Description
第1図は本考案に係るパルス幅変調回路の一実
施例の接続図、第2図は第1図回路の動作波形図
、第3図及び第4図は本考案に係るパルス幅変調
回路の他の実施例の接続図、第5図は従来のこの
種の回路の一例の接続図である。
R1…入力抵抗、C…積分用コンデンサ、CO
P…ヒステリシス・コンパレータ、IV1〜IV
3…インバータ、R2…帰還抵抗。
FIG. 1 is a connection diagram of an embodiment of the pulse width modulation circuit according to the present invention, FIG. 2 is an operation waveform diagram of the circuit shown in FIG. 1, and FIGS. 3 and 4 are diagrams of the pulse width modulation circuit according to the present invention. Connection diagram of another embodiment. FIG. 5 is a connection diagram of an example of a conventional circuit of this type. R1...Input resistance, C...Integration capacitor, CO
P...Hysteresis comparator, IV1 to IV
3...Inverter, R2...Feedback resistor.
Claims (1)
する積分回路、第1の抵抗器と安定した電圧を電
源とする一対のインバータとを従続接続すると共
に第2のインバータの出力端を第2の抵抗器を介
して第1のインバータの入力端に接続してなり前
記積分回路の出力が第1の抵抗器を介して与えら
れるヒステリシス・コンパレータ、及び一端が第
1又は第2のインバータの出力端に接続され他端
が前記積分回路を構成する入力抵抗とコンデンサ
の接続点に接続された帰還抵抗を具備し、第1又
は第2のインバータの出力端よりパルス幅変調信
号を取り出すようにしたパルス幅変調回路。 An integrating circuit that integrates an input voltage is made up of an input resistor and a capacitor, and a first resistor and a pair of inverters whose power source is a stable voltage are connected in series, and the output end of the second inverter is connected to the second resistor. a hysteresis comparator connected to the input terminal of the first inverter via the hysteresis comparator, the output of the integrating circuit being provided via the first resistor, and one end connected to the output terminal of the first or second inverter; and a feedback resistor whose other end is connected to a connection point between an input resistor and a capacitor constituting the integrating circuit, and a pulse width modulation signal is extracted from the output end of the first or second inverter. circuit.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9822487U JPS645533U (en) | 1987-06-26 | 1987-06-26 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9822487U JPS645533U (en) | 1987-06-26 | 1987-06-26 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS645533U true JPS645533U (en) | 1989-01-12 |
Family
ID=31324297
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP9822487U Pending JPS645533U (en) | 1987-06-26 | 1987-06-26 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS645533U (en) |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS58157221A (en) * | 1982-03-13 | 1983-09-19 | Nippon Gakki Seizo Kk | Pulse width modulation circuit |
JPS593611B2 (en) * | 1979-05-17 | 1984-01-25 | 武一 北 | Insulating and dew-proof building materials for prefabricated houses |
-
1987
- 1987-06-26 JP JP9822487U patent/JPS645533U/ja active Pending
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS593611B2 (en) * | 1979-05-17 | 1984-01-25 | 武一 北 | Insulating and dew-proof building materials for prefabricated houses |
JPS58157221A (en) * | 1982-03-13 | 1983-09-19 | Nippon Gakki Seizo Kk | Pulse width modulation circuit |
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