JPH0353038U - - Google Patents
Info
- Publication number
- JPH0353038U JPH0353038U JP11520889U JP11520889U JPH0353038U JP H0353038 U JPH0353038 U JP H0353038U JP 11520889 U JP11520889 U JP 11520889U JP 11520889 U JP11520889 U JP 11520889U JP H0353038 U JPH0353038 U JP H0353038U
- Authority
- JP
- Japan
- Prior art keywords
- transistor
- base
- input signal
- switching
- level
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000003990 capacitor Substances 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 6
Description
第１図は本考案に係るスイツチング回路の一実
施例を示す回路図、第２図はコンデンサの具体的
な構造を示す模式的な断面図、第３図は実施例の
動作を説明するための波形図、第４図乃至第６図
は実施例の動作を説明するための回路図、第７図
はは従来のスイツチング回路を示す回路図、第８
図は入力信号を示す波形図、第９図は従来例の問
題点を説明するための波形図である。
１……入力端子、２……電源端子、３……端子
、４……出力端子、Ｑ１〜Ｑ３……トランジスタ
、Ｒ１〜Ｒ５……抵抗、Ｃ２……コンデンサ。
Fig. 1 is a circuit diagram showing an embodiment of a switching circuit according to the present invention, Fig. 2 is a schematic cross-sectional view showing the specific structure of a capacitor, and Fig. 3 is a diagram for explaining the operation of the embodiment. 4 to 6 are circuit diagrams for explaining the operation of the embodiment, FIG. 7 is a circuit diagram showing a conventional switching circuit, and FIG.
The figure is a waveform diagram showing an input signal, and FIG. 9 is a waveform diagram for explaining problems in the conventional example. 1...Input terminal, 2...Power supply terminal, 3...Terminal, 4...Output terminal, Q1-Q3...Transistor, R1-R5...Resistor, C2...Capacitor.
Claims (1)
定するための基準直流電圧がベースに供給される
第１のトランジスタと、 この第１のトランジスタと共に差動対を成しベ
ースに直流成分を含む入力信号が供給される第２
のトランジスタとを具備し、前記第１又は第２の
トランジスタのコレクタから入力信号の直流レベ
ルに基づく出力信号を出力するスイツチング回路
において、 一端が前記第２のトランジスタのベースに接続
され他端が前記第１のトランジスタのベースに接
続されるコンデンサを具備したことを特徴とする
スイツチング回路。[Claims for Utility Model Registration] A first transistor whose base is supplied with a reference DC voltage for determining the threshold level of switching; and a DC component forming a differential pair with the first transistor; a second input signal provided with an input signal containing
, and outputs an output signal based on the DC level of the input signal from the collector of the first or second transistor, one end of which is connected to the base of the second transistor, and the other end of which is connected to the base of the second transistor. A switching circuit comprising a capacitor connected to the base of the first transistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11520889U JPH0353038U (en) | 1989-09-28 | 1989-09-28 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11520889U JPH0353038U (en) | 1989-09-28 | 1989-09-28 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0353038U true JPH0353038U (en) | 1991-05-22 |
Family
ID=31663546
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11520889U Pending JPH0353038U (en) | 1989-09-28 | 1989-09-28 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0353038U (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5623023A (en) * | 1979-08-01 | 1981-03-04 | Hitachi Ltd | Input buffer circuit |
-
1989
- 1989-09-28 JP JP11520889U patent/JPH0353038U/ja active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5623023A (en) * | 1979-08-01 | 1981-03-04 | Hitachi Ltd | Input buffer circuit |
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